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ics for communications pci interface for telephony/data applications pita-2 psb 4610 version 2.2 preliminary data sheet 01.00 ds 1
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and r epresentatives w orldwide: see our webpage at http:// www.infi neon.com psb 4610 revision history: current version: 01.00 previous version: psb 4610 version 2.1 (12.99) pa ge (in previous ve rsio n) page (in current version) subjects (major changes since last revision) 181 default value (40h) 1221 0001 changed to 1222 0001 abm ? , aop ? , ar c of i ? , arc ofi ? -ba, arcofi ? -sp , di gita pe ? , epic ? -1 , e pic ? -s, elic ? , falc ? 54 , falc ? 56 , fa lc ? -e1 , fa lc ? -lh , idec ? , iom ? , iom ? -1, iom ? -2 , ipa t ? -2, isac ? -p , isa c ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musa c ? -a, octa t ? -p, quat ? - s, sicat ? , sicofi ? , s ic o f i ? -2 , s icofi ? -4, sicofi ? - 4c , sl icofi ? a re re gister ed tra de marks of infine on te chn olo gie s a g. ace ? , as m ? , as p ? , potsw ire ? , qu ad falc ? , s c ou t ? a re tra dem arks of in fine on te ch no log ies a g. dition 01.00 published by infineon technologies ag tr, bala ns tra?e 73, 81 54 1 mnche n ? infine on te chn olo gie s a g 2 000 all rights reserved. attention please! as far a s p aten ts or o ther r igh ts of thir d pa rties are conce rne d, lia bility is onl y a ssu me d fo r comp on ents, not for ap pli ca tion s, pr ocesse s a nd cir cu its i mple men ted with in comp on en ts or a ssemb lies. the i nform ation descri be s the type of co mpo ne nt an d shal l not be co nsid ere d as a ssu red ch ar acteri stics. ter ms o f d elive ry and righ ts to cha ng e de sign r ese rved . due to technical requirements components may contain dangerous substances. for information on the types in qu estion ple ase con tact yo ur n ear est in fi neo n tech no log ies office. infine on te chn olo gie s a g is an app ro ve d ce cc m anu facture r. pa ck ing pl ease u se the r ecycling ope ra to rs known to yo u. we can also h elp yo u ? g et i n touch w ith yo ur n ea rest sale s office. by ag ree men t we will take pa cking m ateri al ba ck, if it is sor te d. yo u must be ar the co sts of tran spor t. for pa cki ng mater ial th at is re turn ed to u s unso rted or which we a re no t obl ige d to accep t, we sha ll h ave to invoi ce you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critica l com pon en ts 1 o f th e in fi ne on te ch no log ies a g, ma y o nly b e used in li fe -sup po rt de vices or system s 2 with the e xp re ss wri tte n ap pro val of the infin eon techn olo gie s ag . 1 a critical component is a component used in a life-support device or system whose failure can reasonably be exp ected to ca use the failu re of th at life -sup por t de vice o r system , or to a ffe ct its safety o r e ffe ctive ne ss of tha t device or system. 2 life support devices or systems are intended (a) to be implanted in the hum an body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- da ng ere d.
psb 4610 preliminary d ata sheet iii 01.00 organization of this data sheet chapter 1, features describes the general features of the pita-2. chapter 2, typical applications with the pita-2 describes typical applications that can be realized with the pita-2. chapter 3, construction of the pita-2 shows a block diagram and describes the interfaces and their functions. chapter 4, communication with the pita-2 describes the pci bus interface of the pita-2. chapter 5, communication with external components gives a general description of the local bus interfaces of the pita-2. chapter 6, power management describes the power management functions (including d3cold) of the pita-2. chapter 7, reset and interrupts describes the requirements for reset and the behaviour of the pita-2. chapter 8, pinning describes the pins, types of pins and the characteristics of the interfaces. chapter 9, electrical characteristics describes electrical maximum ratings and electrical characteristics. chapter 10, package outlines describes the package outlines. chapter 11, configuration space register of the pita-2 contains descriptions of the configuration space registers of the pita-2. chapter 12, internal register of the pita contains descriptions of the internal registers of the pita-2. chapter 13, abbreviations describes abbreviations occuring in this data sheet. chapter 14, index
psb 4610 preliminary d ata sheet iv 01.00 important notes about this data sheet ________________________________________ what?s new? the organization of the structure follows the guidelines of information mapping ? . ________________________________________ what is information mapping ? ? this is a research based method for the ? analysis ? structure ? presentation of user-orientated manuals. ________________________________________ major changes instead of the used chapters with mono causal descriptions you now get ? all information ? for a scope ? under the corresponding heading. ________________________________________ the intention this data sheet is intended to be ? easily surveyed ? increasingly readable ? customized applicable ? practice-orientated ? offering the quickest possible way to the required information. ________________________________________
psb 4610 table of contents page semiconductor group v preliminary data sheet 01.00 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 typical applications with the pita-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 construction of the pita-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 communication with the pita-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 p ci configuration s pace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.1 information about the pci configuration space . . . . . . . . . . . . . . . . . . .12 4.1.2 access to the pci configuration space . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.1.3 b ase address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.1.4 other registers of the pci configuration space . . . . . . . . . . . . . . . . . . . 20 4.2 p ci mas ter/tar get controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.1 supported pci commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.2.2 transaction type burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.2.3 trans action ty pe bur st write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 4.2.4 trans action ty pe fast bac k to b ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3 interrupt control register - retry counter . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 communication with external components . . . . . . . . . . . . . . . . . . . . . .33 5.1 s erial dm a inter face . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.1.1 dm a contr oller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 5.1.2 information about the dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1.3 internal registers of the dma controller . . . . . . . . . . . . . . . . . . . . . . . . .41 5.1.4 iom-2 mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.1.5 iom-2 mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.1.6 iom-2 mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.1.7 iom-2 modes - supplementary description . . . . . . . . . . . . . . . . . . . . . . . 56 5.1.8 single modem mode v2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.1.9 single modem mode alis v3.x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 5.1.10 dual modem/modem+voice mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 5.1.11 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 5.2 p arallel interfac e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 5.2.1 a le after s ystem reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 5.2.2 a le after internal softw are res et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2.3 ale after setting the parallel interface mode bit . . . . . . . . . . . . . . . . . . . 83 5.2.4 non multiplexed mode (write transaction) . . . . . . . . . . . . . . . . . . . . . . . 84 5.2.5 non multiplexed mode (read transaction) . . . . . . . . . . . . . . . . . . . . . . . 86 5.2.6 multiplexed mode (write transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.2.7 multiplexed mode (read transaction) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2.8 transaction disconnect with target abort . . . . . . . . . . . . . . . . . . . . . . . . 89 5.2.9 trans action term ination w ith retry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.2.10 timing of the parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 5.3 general purpose i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
psb 4610 table of contents page semiconductor group vi preliminary data sheet 01.00 5.3.1 information about the gp i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . .98 5.3.2 timing of the gp i/o interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.3 internal registers of the gp i/o interface . . . . . . . . . . . . . . . . . . . . . . .101 5.3.4 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.3.5 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 5.3.6 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.7 usage of the gp i/o interface as alis v2.1 control interface . . . . . . .113 5.4 s pi e eprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.4.1 information about the spi eeprom interface . . . . . . . . . . . . . . . . . . .116 5.4.2 timing of the spi e ep rom inter face . . . . . . . . . . . . . . . . . . . . . . . . . .119 5.4.3 internal registers for the spi eeprom interface . . . . . . . . . . . . . . . . .121 6 p ower managem ent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.1 information about the power supply concept . . . . . . . . . . . . . . . . . . . . . . 124 6.1.1 information about the power management states . . . . . . . . . . . . . . . .126 6.1.2 considerations about power consumption and reporting . . . . . . . . . .128 6.1.3 configuration space registers of the power management . . . . . . . . . .131 6.1.4 e lectr ic al characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.1.5 des ign hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 6.1.6 compatibility issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7 reset and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 7.1 res et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.2 inter rupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 8 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 9.1 a bsolute max im um ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.2 dc charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 10 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 11 configuration space register of the pita-2 . . . . . . . . . . . . . . . . . . . . .173 11.1 des cription of the register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 11.2 configuration space register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 11.3 registers which do not occur elsewhere in the data sheet . . . . . . . . . . .185 12 internal register of the pita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 12.1 des cription of the register types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 12.2 inter nal register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 12.3 registers which do not occur elsewhere in the data sheet . . . . . . . . . . .202 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 14 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
psb 4610 preliminary d ata sheet 1 01.00 introduction ________________________________________ what is the pita-2? the pita-2 is a cost-effective pci bridge for industrial and communication applications. it supports dual cards and d3cold power management. ________________________________________ the pita-2 can be used in pc i isdn cards. pci hardware modems. pci software modems. industrial pci bridge applications. ________________________________________ interfaces of the pita-2 the pita-2 offers the following interfaces: interfaces to find in pci master/target controller see chapter 4.2 on page 22 serial dma interface see chapter 5.1 on page 34 parallel interface see chapter 5.2 on page 78
psb 4610 preliminary d ata sheet 2 01.00 general purpose i/o interface see chapter 5.3 on page 97 spi eeprom interface see chapter 5.4 on page 115 the pita-2 offers the following interfaces: interfaces to find in
psb 4610 features preliminary d ata sheet 3 01.00 1 features ________________________________________ compliant with pc 99 (pci requirements) pci bus specification version 2.2 pci power management specification version 1.1 ________________________________________ highlights dual card support (3.3v and 5v signaling environment) extensive power management features (including d3cold) automatic configuration with customer specific values ________________________________________ interfaces pci master target interface ? pci 2.2 compliant ? 32 bit ? 33 mhz serial interface ? supports iom-2 modes ? supports serial interface to the alis chip-set family ? dma controller for serial communication ? 16 word fifos for each direction parallel interface with chip select logic supporting up to three external components general purpose i/o interface with interrupt capability spi tm inter face for optional eeprom ________________________________________
psb 4610 features preliminary d ata sheet 4 01.00 ________________________________________ compatibility alis v2.1 psb 4596 alis v3.x psb 4596 isdn iom-2 components, e.g.: ? iec-q family ? sbcx, sbcx-x components consisting of a parallel multiplexed or non multiplexed intel/ infineon interface, e.g: ? ipac, ipac-x ? isac-s, isac-sx, isac-sx te ________________________________________
psb 4610 typical applications with the pita-2 preliminary d ata sheet 5 01.00 2 typical applications with the pita-2 ________________________________________ overview besides all the applications that require only a simple pci interface there are some applications which the pita-2 is especially suited for. simple applications benefit from the easy configuration of the pita-2, the extensive power management support and the standard interfaces on the local bus side. telecommunication applications (e.g modems) benefit from the integrated master dma controller as well as the iom-2/gci bus interface. this allows for easy connection of most telecommunications transceivers and substantially reduces the cpu workload. furthermore the pita-2 fully supports d3cold state. this allows the pc to enter a deep sleep state and still be able to react to an incoming call at the same time. ________________________________________ isdn-s interface application with the ipac psb 2115 ipac psb 4610 pta-2 eeprom s0-interface pci bus uc interface spi
psb 4610 typical applications with the pita-2 preliminary d ata sheet 6 01.00 ________________________________________ isdn-u interface application with the 3pac and iec-q te ________________________________________ psb 2113 3pac psb 4610 pta-2 pci bus uc interface eeprom sp i u-interface psb21911 iec-q te
psb 4610 construction of the pita-2 preliminary d ata sheet 7 01.00 3 construction of the pita-2 ________________________________________ overview the pita-2 provides a peripheral component interconnect (pci) bus interface which acts as a bridge between the pci bus and the different controllers and interfaces: the parallel interface control supports up to three external devices. the serial interface is controlled by the internal dma controller; serial communication uses transmit and receive fifos. the eeprom for configuration of the pita-2 and customer specific data storage. the general purpose i/o interface. ________________________________________ block diagram of the pita-2 ________________________________________ pita-2 pc i controller eeprom control parallel interface control serial interface control dma controller tx fifo rx fifo spi- in te rfa ce parallel micr ocontr ol ler in te rfa ce general purpose in te rfa ce se ri al in te rfa ce pci-bus
psb 4610 construction of the pita-2 preliminary d ata sheet 8 01.00 ________________________________________ description of the single blocks name provides supports notes pci bus control a 32 bit interface at speeds up to 33 mhz bus master dma capability for data passing through the serial interface target capability for data passing through the parallel interface d0 d1 d2 d3hot and d3cold 5v environment 3.3v environment vaux supply parallel interface control chips with a infineon/ intel standard parallel interface, including: isdn devices modems dsps industrial devices three prede- coded chip sel- ect lines can be used for pinstrap- ping the subsy- stem/ subsystem vendor id serial interface control chips with a serial interface, including: analog voice codecs analog modem codecs iom-2 devices. transmit and receive data are held in separate 16 word fifos.
psb 4610 construction of the pita-2 preliminary d ata sheet 9 01.00 ________________________________________ eeprom control additional information, such as ? the subsystem id ? the subsystem vendor id ? extensive pow- er manage- ment information all eeproms with spi interface this is an optional feature that can be used to customize the pita-2 configuration at start up. general purpose i/o interface gp outputs gp inputs gp interrupt inputs it can be configured to act as input pins output pins interrupt pins. can be used for pinstrapping the subsystem id description of the single blocks (cont ? d) name provides supports notes
psb 4610 communication with the pita-2 preliminary d ata sheet 10 01.00 4 communication with the pita-2 ________________________________________ ________________________________________ for communication with the pita-2 the following blocks are used: components page pci configuration space 11 pci master/target controller 22 interrupt control register - retry counter 31
psb 4610 communication with the pita-2 preliminary d ata sheet 11 01.00 4.1 pci configuration space ________________________________________ ________________________________________ overview overview page information about the pci configuration space 12 access to the pci configuration space 15 base address register 16 other registers of the pci configuration space 20
psb 4610 communication with the pita-2 preliminary d ata sheet 12 01.00 4.1.1 information about the pci configuration space ________________________________________ description the pci configuration space contains information about the pci device the requested address space in the memory space of the pci system. the address space includes 64 32-bit registers where the first 16 registers build the configuration space header (00h-3ch, refer to ? configuration space register of the pita-2 ? on page 173) ________________________________________
psb 4610 communication with the pita-2 preliminary d ata sheet 13 01.00 ________________________________________ construction of the pci configuration space d evice i d 31 23 15 7 vendor id st at us com mand class code revision id bi st header type latency timer cach line size base address register 0 (internal registers) base address register 1 (parallel interface) base address register 2 (unused) base address register 3 (unused) base address register 4 (unused) base address register 5 (unused) cardbus cis pointer subs ystem i d subsystem vendor id expansion rom base address reserved cap_ptr reserv ed max_lat min_gnt interrupt pin interrupt line power management capabilities capability id next item point er pmcsr bridge support data power data register 1 power data register 2 power data register 3 unused configuration space registers unused configuration space registers shaded fields loaded during initialization if eeprom is connected 58h 54h 50h 4ch 48h 44h 40h 3ch 38h 34h 30h 2ch 28h 24h 20h 1ch 18h 14h 10h 0ch 08h 04h 00h 0 8 16 24 cardbus c is 5ch
psb 4610 communication with the pita-2 preliminary d ata sheet 14 01.00 ________________________________________ ________________________________________ description of register types type description pe read only via pci these bits are initialized by pinstrapping during pci reset or by the optional eeprom h read only via pci hardwired rc read clear via pci these bits are set by the internal logic these bits can be read out and reset by writing logical ? 1 ? to them writing logical ? 0 ? doesn ? t influence the states of these bits rw read write via pci these bits can be read out and written via the pci bus e read only via pci these bits are initialized to a default value during pci reset or by the optional eeprom
psb 4610 communication with the pita-2 preliminary d ata sheet 15 01.00 4.1.2 access to the pci configuration space ________________________________________ description the pita-2 supports single 32 bit data transactions for the access to the pci configuration space. ________________________________________ ________________________________________ special qualities name description subsystem id lower 4 bits can be set via pinstrapping if no eeprom is used with external eeprom the complete 16 bit value can be loaded for the sub system id subsystem vendor id 16 bit id of the card manufacturer has to be applied for at the pci special interest group can be set via pinstrapping during reset if no eeprom is used can be loaded from external eeprom cardbus cis pointer is not supported by the pita-2, although it is implemented in the pci configuration space
psb 4610 communication with the pita-2 preliminary d ata sheet 16 01.00 4.1.3 base address register ________________________________________ ________________________________________ ________________________________________ base address registers 0 - 5 base address register description base address register 0 the lower 12 bits are hardwired to ? 0 ? occupies an address space of 4k allows access to the internal registers of the pita-2 base address register 1 the lower 12 bits are hardwired to ? 0 ? allows continuous read and write operations for access to the parallel interface occupies an address space of 4k address space is logically segmented in 4x1k address blocks base address register 2 - 5 not used structure of the address space of base address register 1 address space access to 3ffh - 000h device 1 on the parallel interface (cs0 ) 7ffh - 400h device 2 on the parallel interface (cs1 ) bffh - 800h device 3 on the parallel interface (cs2 ) fffh - c00h not used
psb 4610 communication with the pita-2 preliminary d ata sheet 17 01.00 ________________________________________ ________________________________________ ________________________________________ configuration space register: 04h bit 1 memory_access_enable type rw d efault value 0b description only if this bit is s et to ? 1 ? , the pci interface will react on transactions to the base address registers bar (all base address registers are defined as memory mapped). configuration space register: 10h bit 31:12 base address register 0 type rw d efault value 0000h bit 11:00 base address register 0 type h value 000h description bar0 contains the base address of an address space in the pci main memory through which the internal registers of the pita-2 can be accessed.
psb 4610 communication with the pita-2 preliminary d ata sheet 18 01.00 ________________________________________ ________________________________________ ________________________________________ configuration space register: 14h bit 31:12 base address register 1 type rw d efault value 0000h bit 11:00 base address register 1 type h value 000h description bar1 contains the base address of a 4-kilobyte address space in the pci main memory through which the parallel micro controller interface of the pita-2 can be accessed. configuration space register: 18h bit 31:0 base address register 2 type h value 0000 0000h description base address register 2 is not supported. configuration space register: 1ch bit 31:0 base address register 3 type h value 0000 0000h description base address register 3 is not supported.
psb 4610 communication with the pita-2 preliminary d ata sheet 19 01.00 ________________________________________ ________________________________________ ________________________________________ configuration space register: 20h bit 31:0 base address register 4 type h value 0000 0000h description base address register 4 is not supported. configuration space register: 24h bit 31:0 base address register 5 type h value 0000 0000h description base address register 5 is not supported.
psb 4610 communication with the pita-2 preliminary d ata sheet 20 01.00 4.1.4 other registers of the pci configuration space ________________________________________ ________________________________________ configuration space register: 28h bit 31:0 cardbus cis pointer type h value 0000 002c0h description unused bit 31:28 rom_image_number type h value 0000b description unused bit 27:3 address_space_offset type h value 000054h description unused bit 2:0 address_space_indicator type h value 000b description unused
psb 4610 communication with the pita-2 preliminary d ata sheet 21 01.00 ________________________________________ note the cardbus function is not supported in this version of the pita-2. ________________________________________ ________________________________________ configuration space register: 2ch bit 31:20 subsystem id type e d efault value 000h bit 19:16 subsystem id type pe value pinstrap value or eeprom value description identifies a specific board of a manufacturer on which the pita-2 is used. the 4 lsbs will be set by pinstrapping gp0-3 during pci reset if no eeprom is used and the complete 16 bit register can be loaded if the optional eeprom is used. bit 15:0 subsystem vendor id type pe value pinstrap value or eeprom value description marks of the vendor of the board on which the pita-2 is used. this register will be set by pinstrapping pad0-7 and pa0-7 during pci reset if no eeprom is used or configured from a connected eeprom. this id is allocated by the pci sig.
psb 4610 communication with the pita-2 preliminary d ata sheet 22 01.00 4.2 pci master/target controller ________________________________________ introduction the interface of the pci bus is represented by the pci master/target controller. this controller is part of the pita-2. the pci master/target controller supports several types of transactions, base address registers 0 and 1. the pci master/target controller has a ? medium device select ? behavior, truncates burst transactions at the end of the first dataphase. ________________________________________
psb 4610 communication with the pita-2 preliminary d ata sheet 23 01.00 4.2.1 supported pci commands ________________________________________ ________________________________________ ________________________________________ pci master controller: pci command transaction type memory read single transfer memory write single transfer pci target controller: pci command transaction type memory read single transfer memory read multiple mapped on memory read memory read line mapped on memory read memory write single transfer memory write and invalidate mapped on memory write configuration read single transfer configuration write single transfer
psb 4610 communication with the pita-2 preliminary d ata sheet 24 01.00 ________________________________________ ________________________________________ note the following timing diagrams are meant as an example and show transactions to and from the pci configuration space. ________________________________________ overview overview page transaction type burst read 25 transaction type burst write 27 transaction type fast back to back 29
psb 4610 communication with the pita-2 preliminary d ata sheet 25 01.00 4.2.2 transaction type burst read ________________________________________ description asserting irdy and stop at the first dataphase leads to the disconnection (disconnect-b) of the burst read transaction by the pita-2. stop is asserted until frame is deasserted. deassertion of frame means that stop and devsel together are deasserted. ________________________________________ timing diagram ________________________________________ adr data 1010 b be 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4610 communication with the pita-2 preliminary d ata sheet 26 01.00 ________________________________________ ________________________________________ configuration space register: 04h bit 26:25 devsel_timing type h value 01b description ? 01 ? = medium timing, i.e. the devsel signal will be asserted from the pci interface with the second positive pci clock edge after frame was asserted on the pci bus by a master.
psb 4610 communication with the pita-2 preliminary d ata sheet 27 01.00 4.2.3 transaction type burst write ________________________________________ description asserting irdy and stop at the first dataphase leads to the disconnection (disconnect-b) of the burst write transaction by the pita-2. stop is asserted until frame is deasserted. deassertion of frame means that stop and devsel together are deasserted. ________________________________________ timing diagram ________________________________________ adr data1 data2 1010 b be1 be2 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4610 communication with the pita-2 preliminary d ata sheet 28 01.00 ________________________________________ ________________________________________ configuration space register: 04h bit 26:25 devsel_timing type h value 01b description ? 01 ? = medium timing, i.e. the devsel signal will be asserted from the pci interface with the second positive pci clock edge after frame was asserted on the pci bus by a master.
psb 4610 communication with the pita-2 preliminary d ata sheet 29 01.00 4.2.4 transaction type fast back to back ________________________________________ description with the fast back to back transaction a pci master controller can perform several write transactions a read transaction as last transaction without setting the pci bus to idle state in between or releasing the bus to another master. at the end of a transaction: the master asserts the frame signal and at the same time the trdy signal is deasserted. the transaction is answered with a retry signal by the pita-2 if the parallel interface is included in the fast back to back transaction and the parallel interface is still busy. ________________________________________ timing diagram ________________________________________ adr data1 adr2 data2 1011 b be1 1011 b be2 12345678910111213 idsel frame irdy trdy devsel ad31-0 c/be3-0 stop
psb 4610 communication with the pita-2 preliminary d ata sheet 30 01.00 ________________________________________ ________________________________________ configuration space register: 04h bit 23 fast_back_to_back_capability type h value 1b description the pita-2 supports fast back-to-back. bit 9 fast_back_to_back_enable type h value 0b description the pita-2 itself generates no fast back-to-back transactions.
psb 4610 communication with the pita-2 preliminary d ata sheet 31 01.00 4.3 interrupt control register - retry counter ________________________________________ description part of the pci master target controller functionality: 1. disconnection of the pci master transaction with retry by the addressed pci slave. 2. decrement of the counter. 3. the retry_counter_int bit is set. 4. an interrupt will be generated if the retry_counter_enable bit is set. 5. the pci master starts the transaction again. ________________________________________ ________________________________________ internal register: 00h bit 27 retry_counter_down_int_en type rw d efault value 0b description enable for the retry_counter_down interrupt bit bit 11 retry_counter_int type rc d efault value 0b description if a pci master initiated transaction is retried from a pci slave with the number of retries defined in the retry_counter register, this interrupt bit is set by the pci interface.
psb 4610 communication with the pita-2 preliminary d ata sheet 32 01.00 ________________________________________ ________________________________________ internal register:1ch bit 23:16 retry count register type rw d efault value 00h description hold the number of retries for a single pci master transaction before the pita-2 will assert an interrupt (if enabled). as an example, if this register is programmed with the value 4, the pita-2 will retry a single pci transaction up to four times as a master before it asserts an interrupt. the pita-2 will continue to retry the transaction until it succeeds or the software decides to abort the whole transaction.
psb 4610 communication with external components preliminary d ata sheet 33 01.00 5 communication with external components ________________________________________ introduction this chapter describes the interfaces for communication with devices on the local bus side (i.e. not the pci bus side). ________________________________________ ________________________________________ interfaces interfaces page serial dma interface 34 parallel interface 78 general purpose i/o interface 97 spi eeprom interface 115
psb 4610 communication with external components preliminary d ata sheet 34 01.00 5.1 serial dma interface ________________________________________ introduction the serial dma interface is used in different modes to transmit and receive 16 bit/ 32 bit data frames. these data frames have different content and structures: data data/voice and command data/voice and command for two codecs different time slots on iom-2. ________________________________________ usage of the s erial dma interface the serial dma interface is clocked by default with the internally generated clock (dcl = pci clock divided by 40). the ser_clock_set bit must be set in the serial clock select register to ? 1 ? when the interface shall work in alis v3.x or iom-2 mode resetting this bit can result in an unknown behavior of the fifos and the serial controller. the serial dma interface is fully controlled by the dma controller. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 35 01.00 ________________________________________ ________________________________________ overview overview page dma controller 36 iom-2 mode 1 47 iom-2 mode 2 50 iom-2 mode 3 53 iom-2 modes - supplementary description 56 single modem mode v2.1 61 single modem mode alis v3.x 65 dual modem/modem+voice mode 73 loop back mode 76
psb 4610 communication with external components preliminary d ata sheet 36 01.00 5.1.1 dma controller ________________________________________ ________________________________________ overview overview page information about the dma controller 37 internal registers of the dma controller 41
psb 4610 communication with external components preliminary d ata sheet 37 01.00 5.1.2 information about the dma controller ________________________________________ description for the control of the dma controller, three register are implemented in the internal registers: the circular buffer start address is a 4-kbyte aligned pci address which points to a 4-kbyte circular buffer in the pci main memory. all dma read/write transactions between host and pita will be processed via this 4-kbyte address space. the dma control register includes the 6-bit parameter dma select which is used to define the mode for the next dma transfer. with the dma_start bit the dma transfer can be started and stopped. the contents of the dma write count register is interpreted as a threshold for the write transfers from the dma controller. ________________________________________ ________________________________________ function of the dma controller phase function 1 dma_start bit is set in the dma control register and a dma transfer is started as defined in the dma select register. 2 the dma controller loads the circular buffer start address to its actual circular buffer pointer. 3 the dma controller fills the tx fifo by reading 15 times through the pci interface (pci master mode) from the circular buffer. 4 the dma controller signals the end of the initial sequence. 5 the dma controller increments the actual circular buffer pointer by 4 each read transfer. 6 the dma controller loads the contents of the 12 bit dma write count register to its internal 12 bit dma write counter. 7 after the first 15 read transfers in the beginning of the 16th read transfer the dma controller starts the normal dma algorithm.
psb 4610 communication with external components preliminary d ata sheet 38 01.00 ________________________________________ ________________________________________ dma write counter after each write transaction from the rx fifo to the buffer the internal dma write counter is incremented by 1. if this counter reaches ? 0 ? an interrupt is generated and the counter is loaded again with the contents of the dma write counter register. the internal dma write counter is decremented every two write transactions as long as two 16 bit values per fsc frame are transferred in the following modes: 32 bit frame mode dual modem mode modem+voice mode iom-2 mode 2 and 3. ________________________________________ function of the dma algorithm phase function 1 the dma controller reads the 16th data word from the current address in the circular buffer (actual circular buffer pointer) to the internal tx fifo. 2 the dma controller writes the first received 16-bit data word from the rx fifo to the same address in the circular buffer. 3 the dma controller increments the actual buffer pointer by 4. 4 the dma controller reads the 17th data word from the current address in the circular buffer (actual circular buffer pointer) to the internal tx fifo. 5 the dma controller writes the second received 16-bit data word from the rx fifo to the same address in the circular buffer. 6 the dma controller increments the actual buffer pointer by 4. 7 and so on
psb 4610 communication with external components preliminary d ata sheet 39 01.00 ________________________________________ dma_start bit the reset of the dma_start bit stops the dma transfer immediately. the assertion of the dma_start bit resets the tx and rx fifo ? s. this means that all fifo data is lost when the dma transfer is stopped. ________________________________________ data in the circular buffer since no data is written from the rx fifo to the circular buffer for the first 15 addresses, the first interrupt after the dma_start assertion means that the received data is available in the circular buffer on address 003ch to 003ch + [dma write count]: 16 bit frame modes 003ch to 0003ch + 2 x [dma write count]: 32 bit frame modes. during normal data transfer every interrupt means that received data is available in the circular buffer on address [end address from last interrupt] to [end address from last interrupt] + [dma write count]: 16 bit frame modes [end address from last interrupt] to [end address from last interrupt] + 2 x [dma write count]: 32 bit frame modes ________________________________________
psb 4610 communication with external components preliminary d ata sheet 40 01.00 ________________________________________ example for dma controlled data transfer via circular buffer the status of the dma controller: 16 bit frame access mode (alis v2.1 mode/iom-2 mode 1) when three data frames are already written to the tx line. ________________________________________ rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch rx data 8 rx data 9 rx data 10 rx data 11 rx data 12 rx data 13 rx data 14 rx data 15 rx data 16 rx data 17 rx data 18 rx data 19 rx data 5 rx data 6 rx data 7 rx data 20 tx data 16 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 19 tx data 18 tx data 17 tx data 4 serial control dma controller pita actual_circular_- buffer_pointer tx fifo rx fifo
psb 4610 communication with external components preliminary d ata sheet 41 01.00 5.1.3 internal registers of the dma controller ________________________________________ internal registers: 00h bit 26 fifo_overflow_empty_int_en type rw d efault value 0b description enable for the fifo_overflow_empty interrupt bit bit 25 dma_write_counter_overflow_int_en type rw d efault value 0b description enable for the dma_write_counter_overflow interrupt bit. bit 24 dma_write_counter_int_en type rw d efault value 0b description enable for the dma_write_counter interrupt bit. bit 10 fifo_overflow_empty_int type rc d efault value 0b description during a dma transfer the serial controller was unable to write received data to the rx fifo because is was already full or the serial controller was unable to send data after the rising fsc edge because of empty tx fifo.
psb 4610 communication with external components preliminary d ata sheet 42 01.00 ________________________________________ bit 9 dma_write_counter_overflow_int type rc d efault value 0b description this bit is set if the internal dma write counter is counted down while the dma_write_counter_int bit is still active. this means that the interrupt generated by the dma_write_counter_int bit is not yet processed. bit 8 dma_write_counter_int type rc d efault value 0b description this bit is set if the number of data, defined in the dma write count register is written through the pci interface. in the 32-bit modes (dual modem, modem+voice, iom-2 mode 2, iom-2 mode 3) this bit is set if the number of data pairs defined in the dma write count register is transferred through the pci interface. internal registers: 00h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 43 01.00 ________________________________________ internal registers: 04h bit 31:0 dma control register bit 31:9 reserved type h value 0000000h description reserved bit 8 dma_start type rw d efault value 0b description by asserting this bit a dma transfer between the circular buffer and the serial dma interface using internal rx/tx fifos is started. this bit is reset by the host if the dma transfer is to be finished. bit 7:6 reserved type h value 00b description reserved
psb 4610 communication with external components preliminary d ata sheet 44 01.00 ________________________________________ bit 5:0 dma select type rw d efault value 000000b description used to define the mode for the next dma transfer: ? mode 1 ( ? 000001 ? ): single modem mode v2.1 ? mode 2 ( ? 000010 ? ): single modem mode v3.x ? mode 3 ( ? 000100 ? ): dual modem/modem+voice mode v3.x ? mode 4 ( ? 001000 ? ): iom-2 mode 1 ? mode 5 ( ? 010000 ? ): iom-2 mode 2 ? mode 6 ( ? 100000 ? ): iom-2 mode 3 with the dma_start bit the dma transfer can be started or stopped. internal registers: 04h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 45 01.00 ________________________________________ ________________________________________ internal registers: 08h bit 31:12 circular buffer start address type rw d efault value 000000h bit 11:0 circular buffer start address type h value 000h description 4-kbyte aligned pci address which points to a 4-kbyte circular buffer in the pci main memory. all dma read/write transactions between the host and the pita are processed via this 4-kbyte address space. internal register: 0ch bit 31:02 actual circular buffer pointer type r value 31-12 equal to 31-12 of register 08, 11-02 actual address bit 1:0 actual circular buffer pointer type h value 00b description by reading this register the software has access to the pci address in the dma circular buffer address pointer. the bits 31-12 are equal the contents of the circular buffer start address register. the bits 11-0 represent the actual dword address in the circular buffer.
psb 4610 communication with external components preliminary d ata sheet 46 01.00 ________________________________________ ________________________________________ internal register: 1ch bit 11:0 dma write count register type rw d efault value 000h description
psb 4610 communication with external components preliminary d ata sheet 47 01.00 5.1.4 iom-2 mode 1 ________________________________________ transmission and reception of data in the circular buffer ________________________________________ dont care b1 31 b2 rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch 15 7 16 8 0 data in circular buffer and on serial dma interface direction data in circular buffer data on serial dma interface transmit bits from circular buffer: [31:16] = don ? t care [15:8] = b1 [7:0] [7:0] = b2 [7:0] write to serial dma interface: b1 [7:0] b2 [7:0]
psb 4610 communication with external components preliminary d ata sheet 48 01.00 ________________________________________ timing diagram ________________________________________ ________________________________________ receive bits to circular buffer: [31:16] = don ? t care [15:8] = b1 [7:0] [7:0] = b2 [7:0] read from serial dma interface: b1 [7:0] b2 [7:0] data in circular buffer and on serial dma interface (cont ? d) direction data in circular buffer data on serial dma interface 8 bit b1 channel du 8 bit b2 channel du 8 bit b1 channel dd 8 bit b2 channel dd 125 us 16 bit b1, b2 frame, double clock fsc (i) dcl (i) txd (o) rxd (i) internal registers: 04h bit 5:0 dma select type rw d efault value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 4 ( ? 001000 ? ): iom-2 mode 1 with the dma_start bit the dma transfer can be started or stopped.
psb 4610 communication with external components preliminary d ata sheet 49 01.00 ________________________________________ ________________________________________ internal register: 20h bit 1 dcl_out_en type rw d efault value 0b description bit 1= ? 0 ? : the dcl signal is configured as input, i.e. not driven by the pita. bit 0 serial_clock_select type rw d efault value 0b description bit 0= ? 1 ? : the serial controller is driven with the external dcl input clock.
psb 4610 communication with external components preliminary d ata sheet 50 01.00 5.1.5 iom-2 mode 2 ________________________________________ transmission and reception of data in the circular buffer ________________________________________ dont care b1 31 b2 rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch 15 7 16 8 0 dont care monitor 0 31 d, c/i, mr, mx 15 7 16 8 0 data in circular buffer and on serial dma interface direction buffer offset data in circular buffer data on serial dma interface transmit 0, 2, 4, ... bits from circular buffer: [31:16] = don ? t care [15:8] = b1 [7:0] [7:0] = b 2 [7:0] write to serial dma interface: b 1 [7:0] b 2 [7:0]
psb 4610 communication with external components preliminary d ata sheet 51 01.00 ________________________________________ timing diagram ________________________________________ transmit 1, 3, 5, ... bits from circular buffer: [31:16] = don ? t care [15:8] = monitor 0 [7:0] [7:0] = d,c/i0,mr,mx [7:0] write to serial dma interface: monitor 0 [7:0] d,c/i0,mr,mx [7:0] receive 0, 2, 4, ... bits to circular buffer: [31:16] = don ? t care [15:8] = b1 [7:0] [7:0] = b 2 [7:0] read from serial dma interface: b 1 [7:0] b 2 [7:0] 1, 3, 5, ... bits to circular buffer: [31:16] = don ? t care [15:8] = monitor 0 [7:0] [7:0] = d,c/i0,mr,mx [7:0] read from serial dma interface: monitor 0 [7:0] d,c/i0,mr,mx [7:0] data in circular buffer and on serial dma interface (cont ? d) direction buffer offset data in circular buffer data on serial dma interface 8 bit b1 channel du 8 bit b2 channel du 8 bit b1 channel dd 8 bit b2 channel dd 125 us 16 bit b1, b2 frame, double clock fsc (i) dcl (i) txd (o) rxd (i) 8 bit monitor 0 channel du 8 bit monitor 0 channel dd 2 bit d 2 bit d 4 bit c/i 0 mr mr 4 bit c/i 0 mx mx 16 bit mon0, d, c/i0, mr, mx frame
psb 4610 communication with external components preliminary d ata sheet 52 01.00 ________________________________________ ________________________________________ ________________________________________ internal registers: 04h bit 5:0 dma select type rw d efault value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 5 ( ? 010000 ? ): iom-2 mode 2 with the dma_start bit the dma transfer can be started or stopped. internal register: 20h bit 1 dcl_out_en type rw d efault value 0b description bit 1= ? 0 ? : the dcl signal is configured as input, i.e. not driven by the pita. bit 0 serial_clock_select type rw d efault value 0b description bit 0= ? 1 ? : the serial controller is driven with the external dcl input clock.
psb 4610 communication with external components preliminary d ata sheet 53 01.00 5.1.6 iom-2 mode 3 ________________________________________ transmission and reception of data in the circular buffer ________________________________________ dont care b1 31 b2 rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch 15 7 16 8 0 dont care ic1 31 ic2 15 7 16 8 0 data in circular buffer and on serial dma interface direction buffer offset data in circular buffer data on serial dma interface transmit 0, 2, 4, ... bits from circular buffer: [31:16] = don ? t care [15:8] = b1 [7:0] [7:0] = b 2 [7:0] bits to serial dma interface: b1 [7:0] b2 [7:0]
psb 4610 communication with external components preliminary d ata sheet 54 01.00 ________________________________________ timing diagram ________________________________________ transmit 1, 3, 5, ... bits from circular buffer: [31:16] = don ? t care [15:8] = ic1 [7:0] [7:0] = ic2 [7:0] write to serial dma interface: ic1 [7:0] ic2 [7:0] receive 0, 2, 4, ... bits to circular buffer: [31:16] = don ? t care [15:8] = b1 [7:0] [7:0] = b 2 [7:0] read from serial dma interface: b1 [7:0] b2 [7:0] 1, 3, 5, ... write to circular buffer: [31:16] = don ? t care [15:8] = ic1 [7:0] [7:0] = ic2 [7:0] read from serial dma interface: ic1 [7:0] ic2 [7:0] data in circular buffer and on serial dma interface (cont ? d) direction buffer offset data in circular buffer data on serial dma interface 8 bit b1 channel du 8 bit b2 channel du 8 bit b1 channel dd 8 bit b2 channel dd 125 us 16 bit b1, b2 frame, double clock fsc (i) dcl (i) txd (o) rxd (i) 8 bit ic1 channel du 8 bit ic1 channel dd 16 bit ic1, ic2 frame 8 bit ic2 channel du 8 bit ic2 channel dd
psb 4610 communication with external components preliminary d ata sheet 55 01.00 ________________________________________ ________________________________________ ________________________________________ internal registers: 04h bit 5:0 dma select type rw d efault value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 6 ( ? 100000 ? ): iom-2 mode 3 with the dma_start bit the dma transfer can be started or stopped. internal register: 20h bit 1 dcl_out_en type rw d efault value 0b description bit 1= ? 0 ? : the dcl signal is configured as input, i.e. not driven by the pita. bit 0 serial_clock_select type rw d efault value 0b description bit 0= ? 1 ? : the serial controller is driven with the external dcl input clock.
psb 4610 communication with external components preliminary d ata sheet 56 01.00 5.1.7 iom-2 modes - supplementary description ________________________________________ selection of iom-2 time slots the misc register contains four bits. they are used for masking the time slot on iom-2. if bx_msk (x := [1,4]) is set: the corresponding value from the tx fifo is not written to the du line. ffh is written to this time slot. in iom-2 mode 1 the bits b3_msk and b4_msk have no effect. data is always transferred from the iom-2 time slot to the rx-fifo. ________________________________________ timing diagram for all iom-2 modes ________________________________________ t fss t fsh t fsw t fsh t wh t wl t cyc t iod t iod fsc (i) dcl (i) rxd (i) txd (o) t fss t iih t iis
psb 4610 communication with external components preliminary d ata sheet 57 01.00 ________________________________________ ________________________________________ figure of the misc register b1 - b4 mask bits ________________________________________ abbreviations for the timing diagram parameter symbol limit values unit min. max. fsc pulse width t fsw 40 ns fsc setup time t fss 40 ns fsc hold time t fsh 40 ns d cl cycle time t cyc 244 ns d cl high tim e t wh 100 ns dcl low time t wl 100 ns iom output data delay t iod 100 ns iom input data setup t iis 20 ns iom input data hold t ii h 20 ns b1 iom-2 mode 1 b2 b1 iom-2 mode 2 b2 monitor 0 d,c/i0,mr,mx b1 iom-2 mode 3 b2 ic1 ic2 misc register: b1_msk b2_msk b3_msk b4_msk
psb 4610 communication with external components preliminary d ata sheet 58 01.00 ________________________________________ masking of iom-2 time slots (example for iom-2 mode 2) ________________________________________ b1 rxd (i) txd (0) b2 monitor 0 b1 b2 monitor 0 previous iom-2 frame don't care b1 b2 don't care monitor 0 d,c/i0,mr,mx d,c/i0,mr,mx d,c/i0,mr,mx next iom-2 frame mon0 b1 d,c/i0, mr,mx b2 mon0 b1 d,c/i0, mr,mx b2 'ffh' 'ffh' 'ffh' 'ffh' rx fifo tx fifo iom-2 dd line iom-2 du line b1_msk b3_msk b4_msk b2_msk data 1 data 1 data 2 data 2 data 3 data 3 circular buffer memory
psb 4610 communication with external components preliminary d ata sheet 59 01.00 ________________________________________ internal register: 1ch bit 31:0 misc (miscellaneous register) bit 31 iom_b1_masking type rw d efault value 0b description bit 31= ? 0 ? : byte b1 is generated out of the circular buffer. bit 31= ? 1 ? : ffh is transmitted on the b1 time slot. bit 30 iom_b3_masking type rw d efault value 0b description bit 30= ? 0 ? : byte b2 is generated out of the circular buffer. bit 30= ? 1 ? : ffh is transmitted on the b2 time slot. bit 29 iom_monitor_0 / ic1_masking type rw d efault value 0b description bit 29= ? 0 ? : byte monitor 0 or ic1 is generated out of the circular buffer. bit 29= ? 1 ? : ffh is transmitted on the monitor/ic1 time slot. monitor is used in iom-2 mode 2. ic1 is used in iom-2 mode 3.
psb 4610 communication with external components preliminary d ata sheet 60 01.00 ________________________________________ bit 28 iom_supl_masking / ic2_masking type rw d efault value 0b description address:= ? 0 ? : byte d, c/i0, mr, mx or ic2 is generated out of the circular buffer. address:= ? 1 ? : ffh is transmitted on the d, c/i0, mr, mx or ic2 tim e slot. d, c/i0, mr, mx: used in iom-2 mode 2. ic2: used in iom-2 mode 3 internal register: 1ch (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 61 01.00 5.1.8 single modem mode v2.1 ________________________________________ ________________________________________ timing diagrams ________________________________________ data in circular buffer and on serial dma interface direction data in circular buffer data on serial dma interface transmit bits from circular buffer: [31:16] = don ? t care [15:0] = data frame [15:0] write to serial dma interface: data frame [15:0] receive bits to circular buffer: [31:16] = don ? t care [15:0] = data frame [15:0] read from serial dma interface: data frame [15:0] 16 bit data 16 bit data 125 us 16 bit data frame fsc (i) dcl (o) txd (o) rxd (i) t fsw t dcd t wh t wl t cyc t dci t isu t iho high-z fsc (i) dcl (o) rxd (i) txd (o) t od
psb 4610 communication with external components preliminary d ata sheet 62 01.00 ________________________________________ ________________________________________ configuration of the single modem mode v2.1 after a system/soft reset the configuration of the psb4596 v2.1 in single modem mode is realized by software using the 4-bit general purpose i/o interface of the pita (see ? general purpose i/o interface ? on page 97.). after a system/soft reset the fsc is an i nput pin both for ? the pita ? the alis v2.1 after a system reset the dc l_out_en bit must be set to ? 1 ? by the host. ________________________________________ abbreviations for the timing diagram parameter sym bol pci clock cycles limit values unit min. typ. max. fsc pulse width t fsw 40 ns dcl delay t dcd 16 480 ns dcl idle time t dci 105 s d cl cycle time t cyc 40 1200 ns d cl high tim e t wh 20 600 ns dcl low time t wl 20 600 ns dcl duty cycle 45 50 55 % input data setup t isu 10 ns input data hold t iho 10 ns output data delay t od 10 ns
psb 4610 communication with external components preliminary d ata sheet 63 01.00 ________________________________________ ________________________________________ note a pull down resistor is required on the board to avoid a floating fsc signal in this situation. ________________________________________ ________________________________________ pita configuration for alis v2.1 after a system reset serial dma interface mode ser_clock_sel (clock input to serial dma interface) dcl_out_en (dcl direction) alis v2.1 0 pc i clock/ 40 1 dcl output internal registers: 04h bit 5:0 dma select type rw d efault value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 1 ( ? 000001 ? ): single modem mode v2.1 with the dma_start bit the dma transfer can be started or stopped.
psb 4610 communication with external components preliminary d ata sheet 64 01.00 ________________________________________ ________________________________________ internal register: 20h bit 1 dcl_out_en type rw d efault value 0b description bit 1= ? 1 ? : the dcl signal is output (open drain) and driven by the pita. bit 0 serial_clock_select type rw d efault value 0b description bit 0= ? 0 ? : the serial controller is driven with the clock signal generated by the internal clock divider.
psb 4610 communication with external components preliminary d ata sheet 65 01.00 5.1.9 single modem mode alis v3.x ________________________________________ ________________________________________ 5.1.9.1 information about the single modem mode alis v3.x ________________________________________ ________________________________________ timing diagram ________________________________________ overview overview page information about the single modem mode alis v3.x 65 internal registers of the single modem mode v3.x 67 data in circular buffers, on serial dma interface direction data in circular buffer data on serial dma interface transmit read from circular buffer: [31:16]= don ? t care [15:0] = data frame [15:0] write to serial dma interface: data frame [15:0] receive write to circular buffer: [31:16]= don ? t care [15:0] = data frame [15:0] read from serial dma interface: data frame [15:0] fsc (i) 16 bit data dcl (i) txd (o) 8 bit cmd 8 bit write data 16 bit data 8 bit read data rxd (i) 125 us 32 bit data / command frame
psb 4610 communication with external components preliminary d ata sheet 66 01.00 ________________________________________ note the timing characteristics of the serial dma interface in single modem mode v3.x mode are identical to the iom-2 modes with the only difference that the dcl signal is not a double bit clock, but a single bit clock, similar to single modem mode v2.1. ________________________________________ configuration of the single modem mode v3.x after a system/soft reset realized by starting the dma transfer. ? separate from this transfer the command byte and command data byte are written to the alis command registers in the pita on addresses 10h. after a system/soft reset the single m odem mode v3.x is in the multiplexed mode because the non multiplexed mode is not supported. the alis v3.x needs some time after an external reset until it has stabilized fsc and dcl. furthermore as the pita-2 does not automatically asserts srst as a response to a pci reset the following procedure is recommended to start the communication with the alis v3.x: ? assert srst by resetting bit 25 of internal register 025h ? deassert srst by setting bit 25 of internal register 025h ? wait 500ms after this procedure the alis v3.x is ready for receiving the first command ________________________________________ ________________________________________ pita configuration for alis v3.x after a system reset serial dma interface mode ser_clock_sel (clock input to serial dma interface dcl_out_en (dcl direction) a lis v3.x 1 dcl input clock 0 dcl_out _en 2 alis v 3.x 1 0 alis v3.x + second codec 10
psb 4610 communication with external components preliminary d ata sheet 67 01.00 5.1.9.2 internal registers of the single modem mode v3.x ________________________________________ ________________________________________ internal registers: 04h bit 5:0 dma select type rw d efault value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 2 ( ? 000010 ? ): single modem mode v3.x with the dma_start bit the dma transfer can be started or stopped. internal register: 10h bit 31:0 alis command register 1 description this command register is used for the first command structure in the fsc time slot by the serial controller. bit 31:25 reserved type h value 0b description reserved
psb 4610 communication with external components preliminary d ata sheet 68 01.00 bit 24 new_alis_command_1 type rw d efault value 0b description bit 24= ? 1 ? : the host has written a new command to the alis command resister 1. bit 24= ? 0 ? : last command written to the alis command register 1 by the host is processed and the received data is available in the alis received data 1 register. this bit is set by software if there is a new command in the alis command 1 register. after the serial dma interface has transmitted the new command and the received data is written to the alis_received_data_1 bits, this bit is reset by the serial dma interface. bit 23:16 alis_received_data_1 type rw d efault value 00h description during a dma transfer in mode 2 or 3 every time a new command is transferred through the serial dma interface, the received data is fetched and saved in this register. new command means: the command was written through the pci interface to the alis command register. transferring a nop command (ffh or 00h) leads to skipping of the received data. internal register: 10h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 69 01.00 ________________________________________ bit 15:8 alis_command_1 type rw d efault value 00h description during a dma transfer in mode 2 or 3 the contents of this register are transferred as command through the serial dma interface. after transferring the new command through the serial dma interface, the register is set to nop (ffh). bit 7:0 alis_transmit_data_2 type rw d efault value 00h description during a dma transfer in alis v3.x mode 2 or 3 the contents of this register are transferred as data through the serial dma interface. internal register: 10h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 70 01.00 ________________________________________ internal register: 14h bit 31:0 alis command register 2 d efault value 00000000h bit 31:25 reserved type h d efault value 000h description reserved bit 24 new_alis_command_2 type rw d efault value 0b description bit 24= ? 1 ? : the host has written a new command to the alis command 2 register. bit 24= ? 0 ? : last command written to the alis command 2 register by the host is processed and the received data is available in the alis received data 2 register. this bit is set by software if there is a new command in the alis command 2 register. after the serial controller has transmitted the new command and the received data is written in the alis received data 2 register, this bit is reset by the serial controller.
psb 4610 communication with external components preliminary d ata sheet 71 01.00 ________________________________________ bit 23:16 alis_received_data_2 type rw d efault value 00h description during a dma transfer in mode 3 every time a new command is transferred through the serial dma interface, the received data is fetched and saved in this register. new command means: the command was written through the pci interface to the alis v3.x command register. if only a nop command (ffh or 00h) is transferred the received data is skipped. bit 15:8 alis_command_2 type rw d efault value 00h description during a dma transfer in mode 3 the contents of this register are transferred as command through the serial dma interface. after transferring the new command through the serial dma interface, the register is set to nop (ffh). bit 7:0 alis_transmit_data_2 type rw d efault value 00h description during a dma transfer in mode 3 the contents of this register are transferred as data through the serial interface. internal register: 14h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 72 01.00 ________________________________________ ________________________________________ internal register: 20h bit 1 dcl_out_en type rw d efault value 0b description bit 1= ? 0 ? : the dcl signal is input and driven by the pita. bit 0 serial_clock_select type rw d efault value 0b description bit 0= ? 1 ? : the serial controller is driven with the external dcl input clock.
psb 4610 communication with external components preliminary d ata sheet 73 01.00 5.1.10 dual modem/modem+voice mode ________________________________________ description the pita transmits and receives two 32 bit frames per fsc time slot. each 32 bit frames consists of 16 bit data and 16 bit command/data information. for each of the 32 bit frames the 16 bit transmitted data is read out of the tx fifo. the 16 bit transmitted data is written to the rx fifo. the command read/write data for the first 32 bit frame is read out/written to the alis command register 1 (10h) the command read/write data for the second 32 bit frame is read out/written to the alis command register 2 (14h). the internal dma write counter is incremented every second write transfer to the circular buffer. a new frame transmission starts if the fsc is sampled ? 1 ? at a negative edge of the dcl signal. the pita starts driving the txd line with the first bit of the transmitted data at the next positive dcl edge. during the transmission the rising dcl edge indicates the start of a bit on the txd while the falling edge of the dcl is used to latch the rxd signal. the pita stops driving the txd signal with the positive dcl edge when bit 32 of the first or second transmitted frame is on the txd line. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 74 01.00 ________________________________________ data organization in the circular buffer ________________________________________ timing diagram for the dual modem mode ________________________________________ rx data 1 tx data 15 tx data 14 tx data 13 tx data 12 tx data 11 tx data 10 tx data 9 tx data 8 tx data 7 tx data 6 tx data 5 tx data 4 tx data 3 tx data 2 tx data 1 rx data 4 rx data 3 rx data 2 tx data 23 tx data 22 tx data 21 tx data 20 don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 15 31 16 0 circular buffer memory 0000h 0004h 0008h 0038h 003ch dont care tx data 1 modem 1 31 15 7 16 8 0 dont care tx data 1 modem 2 31 15 7 16 8 0 16 bit data 8 bit cmd 8 bit write data 16 bit data 8 bit cmd 8 bit write data 16 bit data 8 bit read data 16 bit data 8 bit read data 125 us 32 bit data / command frame 32 bit data / command frame fsc (i) dcl (i) txd (o) rxd (i)
psb 4610 communication with external components preliminary d ata sheet 75 01.00 ________________________________________ timing diagram for the dual modem+voice mode ________________________________________ description of the timing diagram the second 32 bit frame only consists of the 16 bit voice data. the voice data is read out the tx fifo. the voice data is transmitted through the serial dma interface (msb first). during this transmission the received 16 bit voice data (msb first) is written to the rx fifo. ________________________________________ ________________________________________ 16 bit data 8 bit cmd 8 bit write data 16 bit data stuffing pattern 'ffh' 16 bit data 8 bit read data 16 bit data 125 us 32 bit data / command frame 32 bit data frame fsc (i) dcl (i) txd (o) rxd (i) 16 bit stuffing 'ffh' internal registers: 04h bit 5:0 dma select type rw d efault value 000000b description the dma control register includes the 6 bit parameter dma select. used to define the mode for the next dma transfer: mode 3 ( ? 000100 ? ): single dual modem/modem + voice mode v3.x with the dma_start bit the dma transfer can be started or stopped.
psb 4610 communication with external components preliminary d ata sheet 76 01.00 5.1.11 loop back mode ________________________________________ description if loop_back_mode is set to ? 1 ? transmit data is transferred from the tx fifo back to the rx fifo. ________________________________________ mode diagram ________________________________________ pita dma controller tx fifo rx fifo loop closed data 1 data 1 data 2 data 2 data 3 data 3 circular buffer memory serial controller
psb 4610 communication with external components preliminary d ata sheet 77 01.00 ________________________________________ ________________________________________ internal register: 28h bit 0 loop_back_mode type rw d efault value 0b description bit 0= ? 0 ? : the serial controller transmits and receives data/ commands through the serial dma interface (normal operation mode). bit 0= ? 1 ? : the serial controller is in loop back mode. ? the serial dma interface reads the data in the transmitting fifo and writes them in the receiving fifo. ? no data/command transmission will take place on the serial dma interface. ? the serial dma interface is clocked with the defined ser_c lock_sel bit.
psb 4610 communication with external components preliminary d ata sheet 78 01.00 5.2 parallel interface ________________________________________ description the pita has an 8 bit parallel interface to support three external components. this parallel interface is implemented in multiplexed and non multiplexed mode. it works in infineon/intel bus mode. the parallel interface is by default in the non multiplexed mode. ________________________________________ ________________________________________ internal register: 1ch bit 26 parallel_interface_mode type rw d efault value 0b description 0: non multiplexed mode 1: multiplexed mode bit 24 softreset_parallel_mode type rw d efault value 0b description 0: deactivates the reset signal prst to the application. 1: activates the high active reset signal prst to the application.
psb 4610 communication with external components preliminary d ata sheet 79 01.00 ________________________________________ ________________________________________ ________________________________________ mapping between pci data and parallel interface data d ata on the pci bus ad31-0 pci byte enables c/be3-0 data on the parallel interface data bus pad7-0 ad[31-8] = don ? t care ad[7-0] = parallel interface data ? xxx0 ? pad [7-0] = ad [7-0] ad[31-8] = don ? t care ad[7-0] = parallel interface data ? xxx1 ? no transaction, pci interface disconnects with target abort. address mapping of the 4-kbyte pci address space to the parallel interface address on the pci address bus ad11-0 chip select on the parallel interface address on the parallel interface address bus pad7-0 = ad9-2 (mux mode) pa7-0 = ad9-2 (non-mux mode) 3ffh - 000h cs0 ffh - 00h 7ffh - 400h cs1 ffh - 00h bffh - 800h cs2 ffh - 00h fffh - c00h none (not used)
psb 4610 communication with external components preliminary d ata sheet 80 01.00 ________________________________________ ________________________________________ modes and timing of the parallel interface modes and timing page ale after system reset 81 ale after internal software reset 82 ale after setting the parallel interface mode bit 83 non multiplexed mode (write transaction) 84 non multiplexed mode (read transaction) 86 multiplexed mode (write transaction) 87 multiplexed mode (read transaction) 88 transaction disconnect with target abort 89 transaction termination with retry 92 timing of the parallel interface 94
psb 4610 communication with external components preliminary d ata sheet 81 01.00 5.2.1 ale after system reset ________________________________________ timing diagram ________________________________________ description both ale and prst are high during rst and remain high for a maximum of 4 cycles after rst goes deasserted. ________________________________________ 12345678910111213 rst prst ale wr rd
psb 4610 communication with external components preliminary d ata sheet 82 01.00 5.2.2 ale after internal software reset ________________________________________ timing diagram ________________________________________ description after the internal soft reset is deasserted the same behavior as in ? ale after system r eset ? generated. the soft reset bit in the internal registers can only be set or reset if the parallel interface is in idle state. if ale is high before par_rst is asserted, it goes to low one cycle after prst and takes the new value depending on the par_mod bit in the 6 th cycle after prst is deasserted. ________________________________________ prst ale wr rd 12345678910111213
psb 4610 communication with external components preliminary d ata sheet 83 01.00 5.2.3 ale after setting the parallel interface mode bit ________________________________________ timing diagram ________________________________________ description the parallel interface is in non multiplexed mode by default. to set the parallel interface into multiplexed mode: the parallel_interface_mode bit has to be set to ? 1 ? after res et. two pci clocks after finishing this data phase the ale signal is asserted. ________________________________________ 123456789101112 adr data adr1 data cmd1 0000 cmd 0000 ______ frame ____ irdy _____ trdy _______ devsel ad31-0 _______ c/be3-0 _____ stop ale
psb 4610 communication with external components preliminary d ata sheet 84 01.00 5.2.4 non multiplexed mode (write transaction) ________________________________________ timing diagram ________________________________________ description after the address phase on the pci bus (clock3) and the c/be0 =0 verification the address decoding phase of the target (clo cks 3 to 4) is active. the byte address for the transaction on the parallel interface is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0. one pci clock after the pci data phase is finished the data from the pci bus is placed on the data bus pad7-0 (clock 5) and the write transaction starts. the data is placed from the pci bus on pad7-0 asserting the wr signal and a cs2-0 signal. a new access to the parallel interface could be accepted with an address phase at clock 9. any access before would be cancelled with retry because the pci interface is processing the last access. ________________________________________ adr data cmd xxx0 xxxx pci-adr[9-2] xxxx pci-data[7-0] 12 34567 8910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pa7-0 pad7-0
psb 4610 communication with external components preliminary d ata sheet 85 01.00 ________________________________________ example as an example the value 0a4h shall be written at address 005h of the device connected to cs1 . in this example the base address register 1 (bar1) shall contain the address 20004000h. cs1 is activated for the address space 400h to 7ffh. therefore the device ? s address space starts at pci address bar1+400h= 20004400h. only the lower byte of each 32bit word transferred to and from the pita-2 over the pci bus is used for the parallel interface. therefore the relative pci address is four times the relative device address: rel. pci address = four times 005h = 014h. the absolute pci address for the data transfer is bar1+400h+014h=20004414h. only the low byte of a 32 bit data word matters, the upper three bytes are ignored by the pita-2. in order to write the value 0a4h the data word 000000a4 can be written to pci address 20004414h. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 86 01.00 5.2.5 non multiplexed mode (read transaction) ________________________________________ timing diagram ________________________________________ description after the address phase on the pci bus (clock3) and the c/be0 =0 verification the address decoding phase of the target (clo cks 3 to 4) is active. the byte address for the transaction on the parallel interface is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0 (clock 5). the following pci clock asserts the signals rd and cs2-0. after 5 clocks the rd signal is deasserted. the data from pad7-0 is fetched. with the next clock the data is placed on the pci bus and the data phase is finished by deasserting the trdy signal. the 8 bit data from the parallel interface is placed an the last significant byte of the pci data bus ad7-0. ________________________________________ adr data cmd xxx0 xxxx pci-adr[9-2] xxxx data[7-0] 12 345 67 8910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pa7-0 pad7-0
psb 4610 communication with external components preliminary d ata sheet 87 01.00 5.2.6 multiplexed mode (write transaction) ________________________________________ timing diagram ________________________________________ description after the address phase on the pci bus (clock 3) and the c/be0 =0 v erification the address decoding phase of the target (clo cks 3 to 4) is active. the byte address for the transaction on the parallel interface address is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0. one pci clock after the pci data phase is finished the data from the pci bus is placed on the data bus pad7-0 (clock 5) and the write transaction starts. the data is placed from the pci bus on pad7-0 asserting the cs2-0 signal. the ale signal is deasserted. with the following pci clock the data from the pci bus is placed on pad7-0 (clock5). the wr signal is asserted. a new access to the parallel interface could be accepted with an address phase at clock 11. any access before would be cancelled with retry because the pci interface is processing the last access. ________________________________________ adr data1 cmd xxx0 pci-adr[9-2] pci-data1[7-0] 12345 678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4610 communication with external components preliminary d ata sheet 88 01.00 5.2.7 multiplexed mode (read transaction) ________________________________________ timing diagram ________________________________________ description after the address phase on the pci bus (clock 3) and the c/be0 =0 v erification the address decoding phase of the target (clo cks 3 to 4) is active. the byte address for the transaction on the parallel interface is generated out of the pci address ad9-2 by mapping it to the parallel interface address bus pa7-0 (clock 5). the following pci clock asserts the ale signal. after 2 clocks the ale signal is deasserted. the address is held for one more clock. after 5 clocks the rd signal is deasserted. at the same time the data is latched in die pci output registers. trdy is asserted on the pci bus to finish the data phase. at the next clock the cs2-0 and ale signals are deasserted. ________________________________________ adr(00) data1 cmd xxx0 pci-adr[9-2] data1[23-16] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4610 communication with external components preliminary d ata sheet 89 01.00 5.2.8 transaction disconnect with target abort ________________________________________ timing diagram ________________________________________ adr data adr data cmd xxx1 cmd xxx1 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4610 communication with external components preliminary d ata sheet 90 01.00 ________________________________________ description c/be0 = 1: no transaction is started on selected parallel interface, due to the wrong byte enable. the pci master target controller disconnects the transaction with target abort. ________________________________________ configuration space register: 04h bit 30 system_error_signaled type rc d efault value 0b description this bit is set by the pita ? s pci master, if the master asserts the system error signal on the pci bus. this occurs if a transaction initiated by the pita is disconnected with target abort. bit 29 master_abort_detected type rc d efault value 0b description if no fast/medium/slow or subtractive slave reacts to a pci transaction initiated by the pci master, the master will discard the transaction and set this bit. bit 28 master_abort_detected type rc d efault value 0b description if a pci transaction initiated by the pci master is disconnected with target abort, the pci master will set this bit. the pci master is not allowed to start a new pci transaction, until this bit is deasserted.
psb 4610 communication with external components preliminary d ata sheet 91 01.00 ________________________________________ bit 27 target_abort_signaled type rc d efault value 0b description this bit is set by the pci interface if a transaction was disconnected with target abort. the pita will disconnect transactions with target abort if illegal byte enables are detected. bit 8 system_error_enable type rw d efault value 0b description if this bit is asserted, the pci master will assert the system error signal (serr ) if it receives a target abort during a transaction initiated by itself. bit 2 master_enable type rw d efault value 0b description if this bit is set to ? 0 ? the pci master is not allowed to start any transaction on the pci bus. configuration space register: 04h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 92 01.00 5.2.9 transaction termination with retry ________________________________________ description ? retry means that the pita finishes a transaction without a data transfer by asserting the signal stop , because the parallel interface processes another transaction. the pci master target controller has to repeat the transaction until a slave accepts the transaction with data transfer or target abort. this sequence is invisible for the software. ________________________________________ timing diagram ________________________________________ adr1 data1 adr2 data2 cmd1 xxx0 cmd2 xxx0 pci-adr[9-2] pci-data1[7-0] 12345678910111213 frame irdy trdy devsel ad31-0 c/be3-0 stop cs2-0 ale wr rd pad7-0
psb 4610 communication with external components preliminary d ata sheet 93 01.00 ________________________________________ explanation of adr/cmd and adr2/cmd2 adr/cmd: the pci master target controller accepts the write transaction adr2/cmd2: the second transaction is retried. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 94 01.00 5.2.10 timing of the parallel interface ________________________________________ read timing ________________________________________ write timing ________________________________________ multiplexed address timing ________________________________________ rd x cs ad0-ad7 t rr t ri t rd t df data wr x cs ad0-ad7 t ww t wi t wd t dw data ale wr x cs or rd x cs ad0-ad7 t aa t al t la t als t ad address
psb 4610 communication with external components preliminary d ata sheet 95 01.00 ________________________________________ non multiplexed address timing ________________________________________ application reset and interrupt timing ________________________________________ t as t ah address a0-a7 wr x cs or rd x cs vali d s tate prst, srst host write access to the register t rod pr evi ous s tate into (i) t io d inta (o)
psb 4610 communication with external components preliminary d ata sheet 96 01.00 ________________________________________ ________________________________________ abbreviations of the timing diagrams parameter sym- bol pci clock cycles limit values unit min. max . ale pulse width t aa 5 150 ns address setup time to ale t al 130 ns address hold time from ale t la 130 ns address latch setup time to wr , rd t als 130 ns address setup time t as 130 ns address hold time t ah 130 ns ale guard time t ad 130 ns rd pulse width t rr 5 150 ns data output delay from rd t rd 5 150 ns d ata float from r d t df 130ns rd control interval t ri 5 150 ns w pulse width t ww 390 ns d ata s etup tim e to w x cs t dw 260 ns d ata hold tim e w x cs t wd 130 ns w control interval t wi 390 ns r eset output delay t rod 390ns interrupt output delay t iod 260ns
psb 4610 communication with external components preliminary d ata sheet 97 01.00 5.3 general purpose i/o interface ________________________________________ ________________________________________ overview overview page information about the gp i/o interface 98 timing of the gp i/o interface 100 internal registers of the gp i/o interface 101 input mode 107 output mode 109 interrupt mode 111 usage of the gp i/o interface as alis v2.1 control interface 113
psb 4610 communication with external components preliminary d ata sheet 98 01.00 5.3.1 information about the gp i/o interface ________________________________________ description for additional access to external devices with a slow interface behavior a 4 bit general purpose i/o interface is implemented in the pita. ________________________________________ ________________________________________ application interrupt the pci interface supports a separate interrupt input with programmable polarity. the four pins of the general purpose i/o interface can be used as additional interrupt inputs. each of these five interrupts has an interrupt_enable bit and an interrupt_control_status bit. for the separate input the enable an polarity bits are located in the interrupt control register. for the general purpose i/o the enable bits are located in the interface control register. ________________________________________ pinning pin pin name general purpose i/o function spi eeprom function 2 gp0 i/o/int. so 3 gp1 i/o/int. si 4 gp2 i/o/int. sck 5 gp3 i/o/int. ?
psb 4610 communication with external components preliminary d ata sheet 99 01.00 ________________________________________ ________________________________________ control registers for gpx pins register register bit description interrupt control register - icr gpx_int gp interrupt status gp i/o interface control register gpx_int_en gp interrupt enable gpx_out_en gp output enable gpx_out gp output value gpx_in gp input value
psb 4610 communication with external components preliminary d ata sheet 100 01.00 5.3.2 timing of the gp i/o interface ________________________________________ timing diagram ________________________________________ t od valid state host write access gp0-3 (o) gpx configured as output t isu t iho valid state host read access gp0-3 (i) gpx configured as input t iod gpx configured as interrupt input gp0-3 (i) inta (o) abbreviations of the timing diagram parameter symbol limit values unit min. max. gpx output data delay t od 90 ns gpx input data setup t isu 30 ns gpx input data hold t iho 30 ns gpx interrupt output delay t iod 90 ns
psb 4610 communication with external components preliminary d ata sheet 101 01.00 5.3.3 internal registers of the gp i/o interface ________________________________________ internal register: 00h bit 5 gp3_int type rc d efault value 0b description the gp3 pin can be used as ? active low ? interrupt input if gp3_int_en= ? 1 ? and gp3_out_en= ? 0 ? . the bit is set to ? 1 ? if both are true and low is detected at this pin. bit 4 gp2_int type rc d efault value 0b description the gp2 pin can be used as ? active low ? interrupt input if gp2_int_en= ? 1 ? and gp2_out_en= ? 0 ? . the bit is set to ? 1 ? if both are true and low is detected at this pin. bit 3 gp1_int type rc d efault value 0b description the gp1 pin can be used as ? active low ? interrupt input if gp1_int_en= ? 1 ? and gp1_out_en= ? 0 ? .
psb 4610 communication with external components preliminary d ata sheet 102 01.00 ________________________________________ bit 2 gp0_int type rc d efault value 0b description the gp0 pin can be used as ? active low ? interrupt input if gp0_int_en= ? 1 ? and gp0_out_en= ? 0 ? . internal register: 00h (cont ? d) internal register: 18h bit 27 gp3_int_en type rw d efault value 0b description bit 27= ? 1 ? : gp3 is configured as input, the pin is used as an interrupt input with gp3_int_en as corresponding bit in the interrupt control register. bit 27= ? 1 ? : gp3 is not used as an interrupt pin. bit 26 gp2_int_en type rw d efault value 0b description bit 26= ? 1 ? : gp2 is configured as input, the pin is used as an interrupt input with gp2_int_en as corresponding bit in the interrupt control register. bit 26= ? 0 ? : gp2 is not used as an interrupt pin.
psb 4610 communication with external components preliminary d ata sheet 103 01.00 bit 25 gp1_int_en type rw d efault value 0b description bit 25= ? 1 ? : gp1 is configured as input, the pin is used as an interrupt input with gp1_int_en as corresponding bit in the interrupt control register. bit 25= ? 0 ? : gp1 is not used as an interrupt pin. bit 24 gp0_int_en type rw d efault value 0b description bit 24= ? 1 ? : gp0 is configured as input, the pin is used as an interrupt input with gp0_int_en as corresponding bit in the interrupt control register. bit 24= ? 0 ? : gp0 is not used as an interrupt pin. bit 19 gp3_out_en type rw d efault value 0b description bit 19= ? 1 ? : gp_3 is configured as output pin. bit 19= ? 0 ? : gp_3 is configured as input pin. bit 18 gp2_out_en type rw d efault value 0b description bit 18= ? 1 ? : gp_2 is configured as output pin. bit 18= ? 0 ? : gp_2 is configured as input pin. internal register: 18h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 104 01.00 bit 17 gp1_out_en type rw d efault value 0b description bit 17= ? 1 ? : gp_1 is configured as output pin. bit 17= ? 0 ? : gp_1 is configured as input pin. bit 16 gp0_out_en type rw d efault value 0b description bit 16= ? 1 ? : gp_0 is configured as output pin. bit 16= ? 0 ? : gp_0 is configured as input pin. bit 11 gp3_in type r description actual value on the gp3 pin (pin feedback) bit 10 gp2_in type r description actual value on the gp2 pin (pin feedback) bit 9 gp1_in type r description actual value on the gp1 pin (pin feedback) internal register: 18h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 105 01.00 bit 8 gp0_in type r description actual value on the gp0 pin (pin feedback) bit 3 gp3_out type rw d efault value 0b description the gp3 pin is driven with the value written to this output register if the gp3_out_en is set to ? 1 ? . bit 2 gp2_out type rw d efault value 0b description the gp2 pin is driven with the value written to this output register if the gp2_out_en is set to ? 1 ? . bit 1 gp1_out type rw d efault value 0b description the gp1 pin is driven with the value written to this output register if the gp1_out_en is set to ? 1 ? . internal register: 18h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 106 01.00 ________________________________________ bit 0 gp0_out type rw d efault value 0b description the gp0 pin is driven with the value written to this output register if the gp0_out_en is set to ? 1 ? . internal register: 18h (cont ? d)
psb 4610 communication with external components preliminary d ata sheet 107 01.00 5.3.4 input mode ________________________________________ description for using a general purpose i/o pin as input pin, the control register must be configured as follows: gpx_out_en = ? 0 ? (output disabled) gpx_int_en = ? 0 ? (interrupt disabled) (x := [0, 3]) description of the internal register 18h on page 102. the gpx_out and gpx_int bits can be treated as don ? t care in this mode. the current signal value at the pin gpx can be read from register bit gpx_in. ________________________________________ internal structure of a gpx input pin ________________________________________ timing diagram ________________________________________ d q q gpx_in gpx t isu t iho valid state host read access gp0-3 (i) gpx configured as input
psb 4610 communication with external components preliminary d ata sheet 108 01.00 ________________________________________ ________________________________________ abbreviations of the timing diagram parameter symbol limit values unit min. max. gpx input data setup t isu 30 ns gpx input data hold t iho 30 ns
psb 4610 communication with external components preliminary d ata sheet 109 01.00 5.3.5 output mode ________________________________________ description for using a general purpose i/o pin as output pin, the control register must be configured as follows: gpx_out_en = ? 1 ? (output enabled) gpx_int_en = ? don ? t care ? (x := [0, 3]) description of the internal register 18h on page 102. the gpx_in and gpx_int register bits can be treated as don ? t care in this mode. the gpx pin will drive the connected signal line with the value defined in the gpx_out register bit, which is programmed by the host. ________________________________________ internal structure of a gpx output pin ________________________________________ d q q gpx_out en gpx d q q gpx_out_en
psb 4610 communication with external components preliminary d ata sheet 110 01.00 ________________________________________ timing diagram ________________________________________ ________________________________________ t od valid state host write access gp0-3 (o) gpx configured as output abbreviation of the timing diagram parameter symbol limit values unit min. max. gpx output data delay t od 90 ns
psb 4610 communication with external components preliminary d ata sheet 111 01.00 5.3.6 interrupt mode ________________________________________ description for using a general purpose i/o pin as output pin, the control register must be configured as follows: gpx_out_en = ? 1 ? (output disabled) gpx_int_en = ? 1 ? (interrupt enabled) (x := [0, 3]) description of the internal register 18h on page 102. the gpx_out register bit can be treated as don ? t care in this mode. the gpx pin acts as an active low interrupt input pin. if the device detects ? 0 ? at the gpx pin the gpx_int register is set to ? 1 ? an interrupt on the pci bus is generated the current state of the gpx pin can be read from gpx_in bit or can be treated as don ? t care. ________________________________________ internal structure of a gpx interrupt input pin ________________________________________ timing diagram ________________________________________ d q q gpx_in gpx >=1 1 4 3 x 0 inta t iod gpx configured as interrupt input gp0-3 (i) inta (o)
psb 4610 communication with external components preliminary d ata sheet 112 01.00 ________________________________________ ________________________________________ abbreviation of the timing diagram parameter symbol limit values unit min. max. gpx interrupt output delay t iod 90 ns
psb 4610 communication with external components preliminary d ata sheet 113 01.00 5.3.7 usage of the gp i/o interface as alis v2.1 control interface ________________________________________ the serial control interface of the alis v2.1 can be realized by software using the general purpose i/o pins. the gp3 pin is used as cs pin while the other three gpx pins are shared with the spi eeprom interface. the int0 pin of the pita can be programmed to be active on a h level. therefore this pin can be connected directly to the int pin of the alis. the gp3 pin is driven high during the automatic eeprom configuration phase after a system reset to disable the alis v2.1 control interface. pin description on page 162. ________________________________________ ________________________________________ description pita signals alis signals description gp3 out cs chip select (active low), for enabling the psb4596 control interface. gp2 out dclk clock signal for the control interface. (psb4596 accepts 1 khz to 1024 kh z) gp1 in dout data input for pita, data output from psb4596. data input is latched at the negative dclk edge. gp0 out din data output from pita, data input for psb4596. data output changes with the rising dclk edge. int0 in int interrupt signal (high active) srst out reset reset signal (low active)
psb 4610 communication with external components preliminary d ata sheet 114 01.00 ________________________________________ timing diagram for a write transaction with two data bytes transmitted ________________________________________ timing diagram for a read access with one data byte received via dout ________________________________________ gp3 (o) / cs (i) gp2 (o) / dclk (i) gp1 (i) / dout (o) gp0 (o) / din (i) high `z control data byte 1 data byte 2 control frame 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 gp3 (o) / cs (i) gp2 (o) / dclk (i) gp1 (i) / dout (o) gp0 (o) / din (i) high `z control identification data byte 1 control frame 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 6 1 2 3 7 4 5 0 high `z
psb 4610 communication with external components preliminary d ata sheet 115 01.00 5.4 spi eeprom interface ________________________________________ ________________________________________ overview overview page information about the spi eeprom interface 116 timing of the spi eeprom interface 119 internal registers for the spi eeprom interface 121
psb 4610 communication with external components preliminary d ata sheet 116 01.00 5.4.1 information about the spi eeprom interface ________________________________________ description three pins are used to provide an spi tm -compatible serial interface to a 256 x 8 bit eeprom. these pins also do double-duty as part of the general purpose interface. two other pins are also used to select the eeprom chip and to enable/ disable the automatic reconfiguration of the configuration space by the eeprom. this would occur after a system reset. the eeprom can be used for: automatic reconfiguration of the pita. customer specific purposes (e.g. storage of serial board numbers). ________________________________________ automatic reconfiguration of the pita parts of the pci configuration space can be configured with data from this external eeprom after system reset. the following sequence is processed by the pita: the pita checks: ? whether the eld (eeprom_load) pin is clamped to ? 1 ? . ? whether the first byte in the eeprom (address location 00h) is aah. if the first step was successful, the pita starts: ? reading out four bytes starting with address 01h. ? writing the read values in the configuration space address 00h. ? reading out the next four bytes. ? writing the read values in the configuration space address 04h. ? and so on. ________________________________________ note during the configuration phase, all access to the pci interface are answered with ? retry ? by the pita. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 117 01.00 ________________________________________ using the eeprom for customer specific purposes the contents of the eeprom can be programmed by writing a command to the eeprom control register and initiating a read/write transaction to the eeprom. ________________________________________ note if the automatic reconfiguration of the pita is used (eld pin clamped to ? 1 ? ), only those addresses in the eeprom not mapped to the pci configuration space should be used. ________________________________________ starting a read or write transaction the contents of the eeprom can be programmed by writing a command to the eeprom control register and initiating a read/write transaction to the eeprom. the host writes ? the eeprom command value before the next eeprom transfer is started. ? the eeprom byte address value for read or write access. ? the eeprom data value for the ? write status register ? and ? write data to memory array ? . the host sets the eeprom_start bit. if the eeprom interface detects the asserted eeprom_start bit; it ? interprets the eeprom command. starts the read or write transaction to the connected eeprom. if the transactions are started via the eeprom control register, then the eeprom interface does not check for a connected eeprom. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 118 01.00 ________________________________________ after finishing the transaction: the eeprom control module: ? deasserts the eeprom_start bit. ? generates an interrupt in the eeprom control int register, if the eeprom_control_int_en bit is set to ? 1 ? . if the eeprom command register is set to rdsr or read, then the value of the eeprom is available in the eeprom data register. ________________________________________ connection of an alis v2.1 device to the serial control interface for the connection of an alis v2.1 device to the serial control interface of the pita the gp3 pin is additionally used as low active chip select signal cs to the alis v2.1. the gp3 pin is always driven ? high ? and therefore the alis v2.1 interface is inactive during the phase of automatic initialization of the pci configuration space. ________________________________________
psb 4610 communication with external components preliminary d ata sheet 119 01.00 5.4.2 timing of the spi eeprom interface ________________________________________ timing diagram ________________________________________ t css t cyc t clh t cll t isu t iho t csi t csh t or t of t osu t oho t od lsb out lsb in high-z epcs (o) sck (o) so (i) si (o) abbreviations of the timing diagram parameter symbol limit v alues unit min. max. chip select setup time t css 500 ns chip select hold time t csh 500 ns chip select inactive t csi 500 ns c lock cycle time t cyc 1000 ns clock high time t clh 410 ns clock low time t cll 410 ns clock output rise time t or 2s clock output fall time t of 2s input data setup time t isu 100 ns input data hold time t iho 100 ns output data setup time t osu 500 ns
psb 4610 communication with external components preliminary d ata sheet 120 01.00 ________________________________________ note the sck is a strobed clock signal (i.e. it is only active as long as valid data is transferred on si/so line) and output data is written on the falling edge and input data is latched on the rising edge. although the first sck edge is positive, the pita drives the first valid bit on si (output) with the falling edge of epcs , so the minimum setup time with respect to the first sck rising edge is guaranteed. ________________________________________ output data hold time t oho 0 500 ns output disable time t od 500 ns write cycle time t wc 10 ms abbreviations of the timing diagram (cont ? d) parameter symbol limit v alues unit min. max.
psb 4610 communication with external components preliminary d ata sheet 121 01.00 5.4.3 internal registers for the spi eeprom interface ________________________________________ ________________________________________ internal register: 00h bit 28 eeprom_control_int_en type rw d efault value 0b description enable for the eeprom_control_int interrupt bit bit 12 eeprom_control_int type rc d efault value 0b description the eeprom_control_int_en bit and the eeprom are set to ? 1 ? if the transaction is finished. internal register: 24h bit 31:0 eeprom control register d efault value 00000000h bit 24 eeprom_start type rw d efault value 0b description bit 24= ? 1 ? : an eeprom transaction is started with the eeprom command, eeprom data and eeprom byte address. bit 24= ? 0 ? : an eeprom transaction can be started.
psb 4610 communication with external components preliminary d ata sheet 122 01.00 ________________________________________ bit 23:16 eeprom command type rw d efault value 00h description the following spi commands are supported: ? 00000110 ? : wren set write enable latch ? 00000100 ? : wrdi reset write enable latch ? 00000101 ? : rdsr read status register ? 00000001 ? : wrsr write status register ? 00000011 ? : read read data from memory array ? 00000010 ? : wr ite write data to memory array ? others ? : no action bit 15:8 eeprom byte address type rw d efault value 00h description byte address for the next eeprom read or write transaction. bit 7:0 eeprom data type rw d efault value 00h description transaction with a read command: after the transaction has been finished this register contains the byte that has been read from the eeprom. transaction with a write command: the contents of this register will be written to the eeprom byte address if the connected eeprom after the eeprom_start bit is set. internal register: 24h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 123 01.00 6 power management ________________________________________ ________________________________________ overview overview page information about the power supply concept 124 information about the power management states 126 configuration space registers of the power management 131 electrical characteristics 146 compatibility issues 147
psb 4610 p ower managem ent preliminary d ata sheet 124 01.00 6.1 information about the power supply concept ________________________________________ three different power supplies the pita-2 has three different power supplies. it may be helpful for the system design to understand the scope of each of these supplies. vio this supply is internally connected to all signals intended for the pci bus (pin numbers 8-12, 16-60 and 64). vio can be either 3.3v or 5v and is derived from the vio supply of the pci bus. this supply has an effect on the thresholds of the input structure in order to comply with the pci bus specification. therefore the pita-2 can be operated in either 5v or 3.3v signaling environment as specified in the pci local bus specification revision 2.2 vd d3 this supply powers the same pins as listed for vio. it is used for the output drivers of the pci bus signals and must be limited to 3.3v at all times (even when vio is 5v). this supply does not power the internal logic of the pita-2. it does, however, power the local bus signals (pin numbers 1-7, 65-74, 76-87 and 90-100). if this supply is present the input signals on the local bus signals can be as high as 5v. va ux this supply also powers the local bus signals (pin numbers 1-7, 65-74, 76-87 and 90-100) as well as the internal logic. this power supply is 3.3v only. if this supply is not present, the pita-2 can not generate a pme event, the output voltage on any of the above mentioned signals is undefined and the input voltage at any of these pins must not exceed vaux by more than 0.3v. if this supply is present, then the pita is fully operational and the input signals on the local bus signals can be as high as 5v. ________________________________________
psb 4610 p ower managem ent preliminary d ata sheet 125 01.00 ________________________________________ ________________________________________ summary information supply voltage comment vio 3.3v or 5v for pci bus only, affects input threshold, almost no current. should be present at all times. vdd3 3.3v for pci and local bus, decouples internal logic from pci bus. should be present at all times except d3cold. if present, the local bus signals can tolerate 5v. vaux 3.3v supplies internal logic, must be present for 5v tolerance of local (non pci signals) input signals. can be switched off when d3cold is not supported.
psb 4610 p ower managem ent preliminary d ata sheet 126 01.00 6.1.1 information about the power management states ________________________________________ description the pita-2 supports the power management states d0, d1, d2, d3hot and d3cold. the pita-2 can assert the pme signal even if the pci clock (clk) is not running. furthermore the pita-2 has a separate power supply (vaux) which meets the power constraints (20 ma) for the pci vaux supply (disabled slots). therefore the pita-2 fully supports the d3cold state. a separate application note describes a power supply circuitry for a d3cold enabled pita-2. please note that bits 8 (pme_en) and 15 (pme_status) of configuration space register 44h are not affected by a pci reset. this behavior allows the pci device driver to determine the pci device(s) that signalled the pme event. ________________________________________ d0 the d0 state represents the default state of the internal logic after a system reset. after a system reset the pci interface has to be initialized before being used. the pita-2 responds only to configuration accesses while not completely initialized. after initialization the pita-2 is fully operational. ________________________________________ d1 d1 is a light sleep state. the pita-2 supports the d1 state by default if this state is not disabled by an eeprom configuration. the pita-2 pci function can be set to the d1 state by software. the pita-2 pci function only responds to pci configuration accesses. all accesses to the memory spaces defined by the base address registers are disabled. the only pci bus operation the pci interface is allowed to initiate is the assertion of the pme signal. transition to d0 by software is possible. ________________________________________
psb 4610 p ower managem ent preliminary d ata sheet 127 01.00 ________________________________________ d2 by default the support of the d2 state is disabled in the pita-2. d2 can be enabled by configuration by an eeprom. same state behavior as described for the state d1. ________________________________________ d3 same state behavior as described for the state d1. the only legal state transitions from d3 to d0 are: ? by software reset; the software has to perform a fully reinitialization of the pci function including the pci configuration space. ? by system reset ________________________________________ d3hot power and clock are still available to the pita-2. power and clock can be returned to d0 by software. state behavior as described for the state d3. ________________________________________ d3cold (standby) d3cold is a ? power off ? state. the pci clock is turned off. the pci bus power v cc has been disconnected. as long as the pita-2 is supplied with power on the vaux pins it can still assert pme. the pita-2 can assert pme even if the pci clock is not available. ________________________________________
psb 4610 p ower managem ent preliminary d ata sheet 128 01.00 6.1.2 considerations about power consumption and reporting ________________________________________ definitions first of all it is important to distinguish between a pci component and a pci device. the pci component is the circuitry that is interfacing the pci bus. as an example the pita-2 is a pci bus component. the pci device is the circuitry designed to perform a specific function (e.g. a modem) including the pci component. therefore for all power consumption calculations or measurements it is important to add up the power requirements of all the circuitry that is active in a given state. furthermore it is important to distinguish between pci slots that are disabled and those that are enabled. ________________________________________ power consumption a disabled pci slot may draw up to 20 ma from power supply vaux. a pci device which occupies a disabled slot does not have to support d3cold state. as the pita-2 draws a maximum of 19 ma it can be left connected to vaux all the time provided that the external circuitry is switched off (by using the pme_en signal). an enabled pci slot may consume up to 375 ma when in d3cold state. this leaves enough headroom (356 ma) for external circuitry to trigger the pita-2 for a pme event. ________________________________________ reporting the pci bus power management interface specification specifies two ways that allow the operating system or other softw are to determine the power consumption of a pci device: coarse reporting by register 40h:8-6 (aux_current) extended reporting by using the data select mechanism the pita-2 supports both ways. it is up to the pci device designer to choose the reporting mechanism and also which values are reported. extended reporting overrides coarse reporting. ________________________________________
psb 4610 p ower managem ent preliminary d ata sheet 129 01.00 ________________________________________ coarse reporting this mechanism is implemented by the aux current field (register 40h). it is only possible to report a single range for the max. current drawn by the pci device and this range only applied for state d3cold. ________________________________________ assignments ________________________________________ extended reporting this mechanism allows a detailed power consumption reporting. it is possible to report individual power limits for each power state. furthermore there is no predefined range which may fit more or less but all values can be specified by the pci designers as needed. the actual data is retrieved by first selecting a specific item (e.g. d2 power consumed) by writing a select code into the data select field in register 44h. then the pita-2 mirrors the selected values to the data and the data scale field of register 44h. the software can then read these two values. the table below shows the way the data scale field should be interpreted for single function pci devices. 8 7 6 max. current (ma) 1 1 1 375 1 1 0 320 1 0 1 270 1 0 0 220 0 1 1 160 0 1 0 100 0 0155 0 0 0 0 (self powered)
psb 4610 p ower managem ent preliminary d ata sheet 130 01.00 ________________________________________ data selected ? data reported ________________________________________ note the unit for all values is watts. ________________________________________ the data scale field modifies the value of the data field as follows: the actual data can be stored in the external eeprom. at reset the pita-2 loads the data into the appropriate registers. data select d ata reported 0 d0 power consumed 1 d1 power consumed 2 d2 power consumed 3 d3 power consumed 4 d0 power dissipated 5 d1 power dissipated 6 d2 power dissipated 7 d3 power dissipated data scale modifier 0 unknown 1x 0.1 2 x 0.01 3 x 0.001
psb 4610 p ower managem ent preliminary d ata sheet 131 01.00 6.1.3 configuration space registers of the power management ________________________________________ configuration register related to power management there are basically two types of configuration registers related to power management: control registers data registers the control registers (40h and 44h) define the capabilities and the behavior of the pita-2. as an example bit 26 in register 40h defines whether the pita-2 supports d2 or not. the data registers (48h, 4ch and 50h) reflect the power consumption of the whole pci device for eight different configurations. a configuration is selected by a value in the data select field of register 44h. the corresponding value is then placed into the data field of register 44h. the actual values have no effect on the operation or power consumption of the pita-2. these values are calculated or measured by the pci device designer and can be stored in the external eeprom. please note that the pci device includes all external circuitry and usually consists not only of the pita-2. register 34h is merely a pointer to the first register of the power management configuration space and hardwired to 40h. ________________________________________
psb 4610 p ower managem ent preliminary d ata sheet 132 01.00 ________________________________________ ________________________________________ configuration space register: 34h bit 31:8 reserved type h value 000000h description reserved bit 7:0 cap_ptr type h value 40h description the capabilities pointer points to the first power management register in the pci configuration space.
psb 4610 p ower managem ent preliminary d ata sheet 133 01.00 ________________________________________ configuration space register: 40h bit 31:0 power management capabilities (pmc) bit 31 pme_support_d3cold type e d efault value 0b description 0: pme cannot be asserted in state d3cold 1: pme can be asserted in state d3cold bit 30 pme_support_d3hot type e d efault value 0b description 0: pme cannot be asserted in state d3hot 1: pme can be asserted in state d3hot bit 29 pme_support_d2 type e d efault value 0b description 0: pme cannot be asserted in state d2 1: pme can be asserted in state d2
psb 4610 p ower managem ent preliminary d ata sheet 134 01.00 bit 28 pme_support_d1 type e d efault value 1b description 0: pme cannot be asserted in state d1 1: pme can be asserted in state d1 bit 27 pme_support_d0 type e d efault value 0b description 0: pme cannot be asserted in state d0 1: pme can be asserted in state d0 bit 26 d2_support type e d efault value 0b description not supported from the pita-2 by default. support can be enabled by eeprom. bit 25 d1_support type e d efault value 1b description the pita-2 supports the d1 power state by default. can be disabled by eeprom. configuration space register: 40h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 135 01.00 bit 24:22 aux current type e d efault value 000b description this field can be used to report the vaux current drawn by the pci device if the data register in register 44h is not used. if the data register is used, this field must read 000b. otherwise the following assignments apply: 001: up to 55ma 010: up to 100ma 011: up to 160 ma 100: up to 220 ma 101: up to 270 ma 110: up to 320 ma 111: up to 375 ma bit 21 dsi (device specific initialization) type e value 1b description indicates that the pita-2 requires a specific initialization sequence following the transition to d0 state (uninitialized). bit 20 reserved type h value 0b description reserved configuration space register: 40h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 136 01.00 bit 19 pme_clock type e d efault value 0b description the pita-2 can assert pme without a running clock. whether this bit must be set is therefore dependant on the external circuitry that triggers the pita-2 for a pme event. 0: no clock required 1: clock required bit 18:16 version type e d efault value 010b description the value 010b indicates that the device complies with the revision 1.1 of the pci power management interface specification. bit 15:8 next_item_ptr type h value 00h description no next item bit 7:0 capabiltity_id type h value 01h description indicates that the data structure is currently pointed to the pci power management data structure. configuration space register: 40h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 137 01.00 ________________________________________ configuration space register: 44h bit 31:24 data_register type h value 00h description depending on the data_select field (bit 12:9) parts of the power data register (48h) are mapped to this register. bit 23:16 pmcsr_bse (bridge support extension) type h value 00h description not used bit 15 pme_status type rc d efault value none (sticky bit) description this bit is set when the pci interface asserts the pme signal independent of the state of the pme_en bit. bit 14:13 data_scale type h value 00b description depending on the data_select field (bit 12:9) parts of the power_data register are mapped to this register.
psb 4610 p ower managem ent preliminary d ata sheet 138 01.00 bit 12:9 data_select type rw d efault value 0h description values from 0 - 7 are supported: parts of the power_data register are mapped to the data register and the data_scale field. values from 8 - 15: zero values are mapped to the data register and the data_select field. bit 8 pme_en type rw d efault value none (sticky bit) description enables or disables the pita-2 to assert the pme signal. pme_en= ? 0 ? : assertion of the pme signal is disabled. pme_en= ? 1 ? : the device is enabled to assert the pme signal. bit 7:2 reserved type h value 00h description reserved configuration space register: 44h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 139 01.00 ________________________________________ bit 1:0 power_state type rw d efault value 00b description power_state= ? 00 ? : d0 state (supported by the pita-2) power_state= ? 01 ? : d1 state (supported by the pita-2) power_state= ? 10 ? : d2 state (not supported by default) power_state= ? 11 ? : d3hot state (supported by the pita-2). configuration space register: 44h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 140 01.00 ________________________________________ configuration space register: 48h bit 31:30 reserved type h value 00b bit 29:28 data sc ale for data s elec t = 2 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 2. bit 27:20 data for data s elec t = 2 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 2. bit 19:18 data sc ale for data s elec t = 1 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 1.
psb 4610 p ower managem ent preliminary d ata sheet 141 01.00 ________________________________________ bit 17:10 data for data s elec t = 1 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 1. bit 9:8 data sc ale for data s elec t = 0 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 0. bit 7:0 data for data s elec t = 0 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 0. configuration space register: 48h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 142 01.00 ________________________________________ configuration space register: 4ch bit 31:30 reserved type h value 00h bit 29:28 data sc ale for data s elec t = 5 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 5. bit 27:20 data for data s elec t = 5 type e d efault value 00h description this value is mapped to the data field of register 40h when data select (also in register 44h) is set to 5. bit 19:18 data sc ale for data s elec t = 4 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 4.
psb 4610 p ower managem ent preliminary d ata sheet 143 01.00 ________________________________________ bit 17:10 data for data s elec t = 4 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 4. bit 9:8 data sc ale for data s elec t = 3 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 3. bit 7:0 data for data s elec t = 3 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 3. configuration space register: 4ch (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 144 01.00 ________________________________________ configuration space register: 50h bit 31:20 reserved type h value 00b bit 19:18 data sc ale for data s elec t = 7 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 7. bit 17:10 data for data s elec t = 7 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 7. bit 9:8 data sc ale for data s elec t = 6 type e d efault value 00b description this value is mapped to the data scale field of register 44h when data select (also in register 44h) is set to 6.
psb 4610 p ower managem ent preliminary d ata sheet 145 01.00 ________________________________________ bit 7:0 data for data s elec t = 6 type e d efault value 00h description this value is mapped to the data field of register 44h when data select (also in register 44h) is set to 6. configuration space register: 50h (cont ? d)
psb 4610 p ower managem ent preliminary d ata sheet 146 01.00 6.1.4 electrical characteristics ________________________________________ ________________________________________ description of the table the table above shows the current drawn by the v aux power supply in different power management modes. the pita-2 meets the 20ma limit defined for d3cold disabled pci slots. ________________________________________ vaux power supply in different power management modes state typ max d0 19 ma d1 19 ma d2 19 ma d3hot 19 ma d3cold 19 ma
psb 4610 p ower managem ent preliminary d ata sheet 147 01.00 6.1.5 design hints ________________________________________ d3cold for a design that supports d3cold it is important to check all signals on the local bus side of the pita-2 that may be affected by a missing vdd3. as during d3cold vdd3 will drop to zero all pins that are strapped to vdd3 either directly or by a pullup will also drop to zero. therefore it is strongly recommended to strap pins on the local bus side of the pita-2 to vaux instead. this is especially important for the test pin (pin 1) of the pita-2. if this pin is not kept at a high level during d3cold the pita-2 will not be able to reliably assert pme#. pins that can cause an interrupt (int0 and gp0-gp3) should also be checked to avoid unwanted pme# events. ________________________________________
psb 4610 p ower managem ent preliminary d ata sheet 148 01.00 6.1.6 compatibility issues ________________________________________ supported designs by pita the pita-2 supports designs which are compliant to the pci local bus specification revision 2.2 and the pci bus power management interface specification revision 1.1 . ________________________________________ potential compatibility problem the only potential compatibility problem arises if the pita-2 is used in a design which: uses the pme signal does not support d3cold in this case it may be tempting to connect the vaux power supply of the pita-2 directly to the 3.3v signal of the pci connector and likewise directly connect the pme signal of the pita-2 to the pme# signal of the pci connector. however, such a design may affect a pci system, which: supports vaux has at least one device with d3cold support connected under these circumstances the following unwanted behavior may happen: the pci system enters d3cold and the pci bus enters state b3. in this state the supply power 3.3v is disabled while vaux remains active. as the pita-2 is connected to the 3.3v supply its own supply vaux will also float. the pme signal of the pita-2 has an internal clamp diode which will limit the voltage on pme to about vaux+0.7v. therefore it is likely that the pita-2 will pull down the pme# signal and therefore block all other d3cold compliant devices on the bus. this behavior can be easily avoided by implementing vaux detection and power switching as the pita-2 meets the power supply requirements for pci slots that do not support d3cold but have vaux power supply. if the pci device cannot generate a pme event at all it is best to leave the pme# signal of the pci connector not connected. ________________________________________
psb 4610 reset and interrupts preliminary d ata sheet 149 01.00 7 reset and interrupts ________________________________________ 7.1 reset ________________________________________ introduction after each power up the pita-2 must be reset. this reset is necessary to establish a well defined state for all subsequent actions. this chapter informs about: reset phases external signals affected by reset internal registers affected by reset pinstrapping automatic reconfiguration ________________________________________ reset phases the pita-2 can be only reset by pulling the rst signal low and then high while the pita-2 is powered up. there is no provision for a power on reset. furthermore the pita-2 requires seven clock cycles after the rising edge of the rst signal. after the rising edge the pita-2 may start the automatic reconfiguration. during this process it copies the contents of an external eeprom into selected fields of the configuration space registers. automatic reconfiguration is entered when signal eld is strapped to h. otherwise the pita-2 will skip this phase. ________________________________________
psb 4610 reset and interrupts preliminary d ata sheet 150 01.00 ________________________________________ external signals all pci signals are floated as long as the rst signal is low. significant input signals (gpio0-gpio3, pa0-pa7, pad0-pad7 and eld) must remain stable at least six clock cycles after the rising edge of the rst signal. the signal prst is forced to low (inactive state) at the rising edge of rst . the signal srst is forced to high (inactive state) at the rising edge of rst . usually both signals have not been active before the rst signal has been asserted. therefore no signal change will usually happen at both srst and psrt. as a consequence components which are connected to one of these signals are not automatically reset by a pci reset. this behavior is desirable when these components remain active during d3cold because after a wake up the sw driver can obtain valuable information from these devices about the reason for a wake up. on the other hand, for a complete initialization of the pci device the sw driver must perform a reset for these devices by specifically programming the internal registers of the pita-2. ________________________________________ internal registers all internal register fields that are affected by an external reset are marked by a default value in the register description. this default value may be overridden by the optional automatic reconfiguration process. after an external reset the pita-2 allows only configuration space accesses. furthermore the pita-2 will abort configuration space accesses until it has completed the reset sequence (including the optional automatic reconfiguration process). therefore the sw driver will not be able to read any incorrect transient value from any configuration space register. for the power management the following bits are not affected by an external reset (sticky bits): configuration space 44h:8 configuration space 44h:15 internal register 18h:24-27 the reason for this behavior is that the pita-2 supports the d3cold state and thus must be able to assert a pme signal even while rst is low. ________________________________________
psb 4610 reset and interrupts preliminary d ata sheet 151 01.00 ________________________________________ pinstrapping pinstrapping is used for: loading the subsystem vendor id. loading the least significant 4 bits of the subsystem id to the pci configuration space. several output pins from the parallel micro controller interface and the general purpose i/o interface are implemented as tristate output pins. during pci reset they are driven in tristate mode and the external logic value is latched in the subsystem id (4 lsbs) and the subsystem vendor id. this means that the signals on board, connected to these pins, must be forced with pullup/ pulldown resistors to the desired value if they are not driven by the pita-2. ________________________________________ automatic reconfiguration of the pita-2 with the serial eeprom the pita-2 can also be configured by the eeprom after system reset. pinstrap values are overwritten by this process if the procedure described in ? autom atic reconfiguration of the pita ? on page 116 was successful. the pita-2 will abort pci configuration accesses during automatic reconfiguration. ________________________________________ signal name usage during pci reset (pinstrapping) pad(7:0) subsystem vendor id(15:8) pa(7:0) subsystem vendor id(7:0) gp3 subsystem id(3) gp2 subsystem id(2) gp1 subsystem id(1) gp0 subsystem id(0)
psb 4610 reset and interrupts preliminary d ata sheet 152 01.00 7.2 interrupts ________________________________________ introduction the pita-2 can generate an interrupt on the pci signal inta external, asynchronous event (e.g. an incoming call) internal, synchronous event (e.g. an eeprom access finished)) ________________________________________ general notes the pita-2 can only assert inta if the following requirements are met: pita-2 is in d0 or d1 state the interrupt source is enabled by setting the corresponding interrupt enable bit in internal register 00h (icr). the event has occurred once inta has been asserted by the pita-2 it will stay active until a write transaction to the internal register icr occurs. after this write transaction has occurred the pita-2 deasserts the signal inta . the pita-2 will immediately after this write transaction assert inta again if either of the following conditions holds: not all interrupt reporting bits have been cleared the requirements for asserting an interrupt still hold the former condition usually arises when more than one source has been activated and the interrupt handler reacts to the events sequentially. the latter condition usually arises if an external event has occurred a second time while the interrupt handler is still processing the first occurrence of this event. reporting bits within the internal register icr can only be cleared by writing a logical 1 at the bits that shall be cleared. a read access to this register does not clear any bit nor does it affect any signal. ________________________________________
psb 4610 reset and interrupts preliminary d ata sheet 153 01.00 ________________________________________ external events for external events either the dedicated int0 pin or one of the general purpose io pins (gp0-gp3) can be used. the following table shows how to program the pita-2 in order to activate one or more of these pins for interrupts. ________________________________________ ________________________________________ programming of the pita-2 source enabled by reported by active level int0 00h:int0_en=1 00h:int0_pol=1 00h:int0=1 h int0 00h:int0_en=1 00h:int0_pol=0 00h:int0=1 l gp0 00h:gp0_int=1 18h:gp0_int_en= 1 18h:gp0_out_en = 0 00h:gp0_int=1 l gp1 00h:gp1_int=1 18h:gp1_int_en= 1 18h:gp1_out_en = 0 00h:gp1_int=1 l gp2 00h:gp2_int=1 18h:gp2_int_en= 1 18h:gp2_out_en = 0 00h:gp2_int=1 l gp3 00h:gp3_int=1 18h:gp3_int_en= 1 18h:gp3_out_en = 0 00h:gp3_int=1 l
psb 4610 reset and interrupts preliminary d ata sheet 154 01.00 ________________________________________ internal events the following internal events can trigger an interrupt when enabled: an eeprom command has finished the programmed number of writes to the dma buffer has occurred fifo overflow (receive failure) fifo underflow (transmit failure) the pci retry counter has expired (too many retries for a single transfer) ________________________________________ ________________________________________ eeprom command finished & dma watermark reached the eeprom command finished and the dma watermark reached interrupts are normal events. ________________________________________ fifo overflow & fifo underflow the fifo overflow and fifo underflow events indicate a fatal error which may result in a communication failure. the actual impact of these events depends on the error detection and error correction capabilities of the communication protocol of the application. ________________________________________ summation of the used bits in register icr event enabled by reported by eeprom command finished 00h:28=1 00h:12=1 dma watermark reached 00h:24=1 00h:8=1 fifo overflow 00h:25=0 00h:9=1 fifo underflow 00h:26=1 00h:10=1 pci retries expired 00h:27=1 00h:11=1
psb 4610 reset and interrupts preliminary d ata sheet 155 01.00 ________________________________________ pci retries expired the pci retries expired event is not a normal event but is not necessarily a fatal event. if the pita-2 reports this event the following has happened: the dma controller has requested a data word transfer to/from the fifo. the pita-2 has requested the pci bus for the transfer. the pita-2 has been granted the pci bus. the pita-2 has initiated the transfer times but the pci target has aborted the transfer each time. is the number programmed in internal register 1ch:23:16. at this point the pita-2 releases the pci bus and reports the event. however, as the dma data transfer request is not satisfied the pita-2 will request the pci bus again for the same data transfer until the request is satisfied. depending on the pci target this may either have no effect (data delivered in time finally) or a fatal event may happen (fifo overflow/underflow). ________________________________________ caution it is important to bear in mind that in d3cold state vdd3 will vanish. for devices that support d3cold it is therefore strongly recommended to strap low active interrupt sources (e.g. gp0-gp3) not to vdd3 but to vaux instead. ________________________________________
psb 4610 pinning preliminary d ata sheet 156 01.00 8pinning ________________________________________ pita-2 pinout this illustration shows the numbered pins and their respective signals: ________________________________________ pita-2 t-qfp-100-10 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 cs1 cs2 inta vaux vss vio vdd3 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 c/b e0 ad8 ad9 ad1 0 ad1 1 ad1 2 ad1 3 ad1 4 ad15 c/ be1 par serr perr stop devsel t rdy irdy frame c/ be2 ad1 6 ad1 7 ad1 8 ad1 9 ad2 0 ad2 1 ad2 2 ad2 3 prst pad7 pad6 pad5 pad4 pad3 pad2 pad1 pad0 rd cs0 wr vaux vss pm e_en ale int0 srst dcl rxd txd fsc vaux_pr eld ecs gp3 tes t gp2 gp1 gp0 cl kru n pme rs t clk gnt req vaux vss vio vdd3 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 idsel
psb 4610 pinning preliminary d ata sheet 157 01.00 ________________________________________ overview the following table lists the interfaces and their respective pins: ________________________________________ ________________________________________ interface total in out i/o page pci bus 52 4 5 43 158 parallel interface 23 3 14 8 159 serial interface 5 2 2 1 161 gp i/o interface 4 0 0 4 162 special eeprom signals 2 1 1 0 163 power management 2 1 1 description of pin types type description o/ps output pin/pin strap pin i input pin io bidirectional input/output pin od open drain
psb 4610 pinning preliminary d ata sheet 158 01.00 ________________________________________ this table lists the pins characteristics of the pci bus pin no. signal name pin count type function 9 clk 1 i pci - clock (max. 33 mhz) 8rst 1ipci - reset 16 - 23, 26 - 33, 44 - 51, 53 - 60 ad(31:0) 32 io pci - address-/data bus 24, 34, 43, 52 c/be (3:0) 4 io pci - command/byte enable bus (byte enables are low active) 42 par 1 io pc i - parity 64 inta 1 od pci - interrupt signal 25 idsel 1 i pci - initialization device select signal for cardbus boards this signal must set to ? 1 ? 35 frame 1iopci - frame 36 irdy 1 io pci - initiator ready 37 trdy 1 io pci -target ready 38 devsel 1 io pc i - device select 39 stop 1iopci - stop 11 req 1 ots pci - bus request 10 gnt 1 i pci - bus grant
psb 4610 pinning preliminary d ata sheet 159 01.00 ________________________________________ 40 perr 1 io pc i - parity error 41 serr 1 od pc i - system error 7pme 1 od pc i - power management event 12 clkrun 1 i clock run this table lists the pins characteristics of the pci bus (cont ? d) pin no. signal name pin count type function this table lists the pins characteristics of the parallel interfaces pin no. signal name pin count type function 76 prst 1 o active high reset 66, 67, 87 cs (2:0) 3 o chip select signals for three devices connected to the parallel micro controller interface. 84 - 77 pad(7:0) 8 io - multiplexed bus mode: address/data bus for the parallel interface. - non-multiplexed bus mode: data bus for the parallel interface.
psb 4610 pinning preliminary d ata sheet 160 01.00 ________________________________________ 74 - 68, 65 pa(7:0) 8 o/ps - multiplexed bus mode: not used; pins can be left not connected. - non-multiplexed bus mode: address bus for the parallel interface. 91 ale 1 o address latch enable signal, active high. in non-multiplexed mode the ale input of peripheral devices must be connected to vss. 86 wr 1 o write signal, active low 85 rd 1 o read signal, active low 92 int0 1 i standard active low interrupt input for connected devices, which is forwarded to the pci interface (inta ). this table lists the pins characteristics of the parallel interfaces (cont ? d) pin no. signal name pin count type function
psb 4610 pinning preliminary d ata sheet 161 01.00 ________________________________________ ________________________________________ this table list the pins characteristics of the serial interface pin no. signal name pin count type function 93 srst 1 o active low reset output. 97 fsc 1 i frame synchronization clock signal, 8 khz. 94dcl1i o (od) serial data clock signal. the direction of this pin can be controlled by the dcl_out_en bit in the internal registers. by default this pin is input. for psb4596 v2.1 mode, this pin must configured as output (open drain), for all other modes this pin must be input. 95 rxd 1 i serial data input signal 96 txd 1 o (od) serial data output signal
psb 4610 pinning preliminary d ata sheet 162 01.00 ________________________________________ ________________________________________ this table lists the pins characteristics of the general purpose i/o interface pin no. signal name pin count type function 2 gp3 1 io general purpose i/o pin 3 this pin is driven high during the automatic eeprom configuration if eld = ? 1 ? . 3 gp2 1 io general purpose i/o pin 2 serial eeprom interface: sck - serial clock signal. 4 gp1 1 io general purpose i/o pin 1 serial eeprom interface: so - serial data output from eeprom (input to the pita-2). 5 gp0 1 io general purpose i/o pin 0 serial eeprom interface: si - serial data input to the eeprom (output from the pita-2).
psb 4610 pinning preliminary d ata sheet 163 01.00 ________________________________________ ________________________________________ this table lists the pins characteristics of the special eeprom signals pin no. signal name pin count type function 99 eld 1 i eeprom load ? 1 ? -> eeprom configuration is enabled. ? 0 ? -> eeprom configuration is disabled. 100 ecs 1 o eeprom chip select (spi signal)
psb 4610 pinning preliminary d ata sheet 164 01.00 ________________________________________ this table lists the pins characteristics of the power management pin no. signal name pin count type function 90 pme_en 1 o reflects the state of the pme_en bit. can be used to power down all external logic that is not needed in state d3. 98 vaux_pr 1 i indicates that vaux is present.
psb 4610 pinning preliminary d ata sheet 165 01.00 ________________________________________ ________________________________________ this table lists the pins characteristics of the power supply pin no. signal name pin count type function 15, 61 vdd3 5 i positive power supply 3.3v 10% 6, 75, 88 vaux 3 i positive power supply 3.3v 10% 14, 62 vio 2 i io voltage supply (either 3.3v or 5v) 13, 63, 89 vss 3 i ground 0v
psb 4610 electrical characteristics preliminary d ata sheet 166 01.00 9 electrical characteristics ________________________________________ ________________________________________ pin groups the pita-2 has two different kind of pins: pc i pins (8-12, 16-60 and 64) these pins are powered by vdd3 and vio and are intended for connection to the pci bus. local pins (1-5, 7, 65-74, 76-87 and 90-100) these pins are powered by vaux or vdd3 (one power supply is sufficient) and are intended for connection to the local signal of the pci device. the ac and dc specification for these two groups are may be different and are therefore listed in separate tables for each group. ________________________________________ overview: overview page absolute maximum ratings 167 dc characteristics 168
psb 4610 electrical characteristics preliminary d ata sheet 167 01.00 9.1 absolute maximum ratings ________________________________________ ________________________________________ note: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage to the device. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. this is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. ________________________________________ this table shows the parameters for the absolute maximum ratings parameter limit v alues unit voltage on pci pins with respect to ground v s1 ? 0.5 to v io + 0.5 v voltage on local pins with respect to ground v s2 ? 0.3 to 5.5 v ambient temperature under bias t a 0 to 70 c storage temperature t stg ? 65 to 150 c maximum voltage on vio v dd 7v maximum voltage on vdd3 and vaux v dd 4.6 v
psb 4610 electrical characteristics preliminary d ata sheet 168 01.00 9.2 dc characteristics ________________________________________ description the dc characteristics of the pita-2 are given in three separate tables: pci pins, 5v signaling environment (vio = 5v) pci pins, 3.3v signaling environment (vio = 3.3v) local pins ________________________________________ conditions 5v signaling environment t a = 0 to 70 c; v io = 4.75v to 5.25v, v au x and v dd3 = 3.0v to 3.6v, v ss = 0 v 3.3v signaling environment t a = 0 to 70 c; v io , v aux and v dd3 = 3.0v to 3.6v, v ss = 0 v ________________________________________
psb 4610 electrical characteristics preliminary d ata sheet 169 01.00 ________________________________________ ________________________________________ dc characteristics pci pins (5v signaling environment) parameter sym limit values unit test condition rem. min max input high voltage v ih 2.0 v io + 0.5 v input low voltage v il ? 0.5 0.8 v input high leakage current i ih 70 ua vin = 2.7v 1) input low leakage current i il -70 ua vin = 0.5v 2) output high voltage v oh 2.4 v i oh = ? 2ma l-output voltage v ol 0.55 v i ol = 3/6 ma 3) input pin capacitance c in 10 if pin inductance l pin 20 nh pme# input leakage i of f 1 ua vout below 5.25v vd d3 off/floating 1) except for clkrun which i s in te rn ally pu lle d do wn (i lih = 50 0 ua 2) except for clkrun which i s in te rn ally pu lle d do wn (i lih = 50 0 ua 3) 6m a for fra me, trdy , ir dy , devsel , stop , serr , perr , lock and inta
psb 4610 electrical characteristics preliminary d ata sheet 170 01.00 ________________________________________ ________________________________________ dc characteristics pci pins (3.3v signaling environment) parameter sym limit v alues unit test condition rem. min max input high voltage v ih 0.5v io v io +0.5 v input low voltage v il ? 0.5 0.3v io v input leakage current i il -10 10 ua 0 < vin < v io 1) output high voltage v oh 0.9v io vi oh = ? 0.5 ma l-output voltage v ol 0.1v io vi ol = 1.5ma input pin capacitance c in 10 pf pin inductance l pin 20 nh pme# input leakage i off 1 ua vout below 3.6v vdd3 off/ floating 1) except for clkrun which i s in te rn ally pu lle d do wn (i lih = 50 0 ua
psb 4610 electrical characteristics preliminary d ata sheet 171 01.00 ________________________________________ ________________________________________ dc characteristics local pins parameter sym limit v alues unit test condition rem. min max input high voltage v ih 2.4 5.25 v input low voltage v il ? 0.3 0.8 v input leakage current i il -10 10 ua output high voltage v oh 2.4 v i oh = ? 2 ma l-output voltage v ol 0.4 v i ol = 2 ma
psb 4610 package outlines preliminary d ata sheet 172 01.00 10 package outlines
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 173 01.00 11 configuration space register of the pita-2 ________________________________________ ________________________________________ overview page description of the register types 174 configuration space registers 175 registers which do not occur elsewhere in the data sheet 185
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 174 01.00 11.1 description of the register types ________________________________________ ________________________________________ description of the register types type description pe read only via pci these bits are initialized by pinstrapping during pci reset or by the optional eeprom h read only via pci hardwired rc read clear via pci these bits are set by the internal logic these bits can be read out and reset by writing logical ? 1 ? to them writing logical ? 0 ? doesn ? t influence the states of these bits rw read write via pci these bits can be read out and written via the pci bus e read only via pci these bits are initialized to a default value during pci reset or by the optional eeprom
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 175 01.00 11.2 configuration space registers ________________________________________ ________________________________________ 00h ad. bit type default value register name page 00h 31:16 e 2104h device id 185 15:0 e 110ah vendor id of siemens ag. 185 04h ad. bit type default value register name page 04h 31:0 0290 0000h pci status register 185 31 rc 0b parity error d etected 185 30 rc 0b system error signaled 90 29 rc 0b master abort detected 90 28 rc 0b target abort detected 90 27 rc 0b target abort signaled 90 26:25 h 01b devsel timing 26 28 24 rc 0b data parity error reported 185 23 h 1b fast back-to-back capability 30 22 h 0b user defined functions 185 21 h 0b 66 mhz capability 185
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 176 01.00 ________________________________________ 20 e 1b capabilities 185 19:16 h 0000b reserved 185 15:0 command register 185 15:10 h 000000b reserved 185 9 h 0b fast back-to-back enable 30 8 rw 0b system error enable 90 7 h 0b address/data stepping enable (not used) 185 6 rw 0b parity error response 185 5:3 h 000b the pita-2 does not support the special cycle command. 185 2 rw 0b master enable 90 1 rw 0b memory access enable 17 0 h 0b i/o access enable 185 04h (cont ? d) ad. bit type default value register name page 08h ad. bit type default value register name page 08h 31:8 e 028000h class code/pci network device 188 7:0 e 02h revision id 188
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 177 01.00 ________________________________________ ________________________________________ ________________________________________ ________________________________________ 0ch ad. bit type default value register name page 0ch 31:24 h 00h bist 189 23:16 h 00h header type 189 15:8 h 00h master latency timer 189 7:0 h 00h cache line size 189 10h ad. bit type default value register name page 10h 31:0 31:12 11:0 rw h 00000000h base register 0 17 14h ad. bit type default value register name page 14h 31:0 31:12 11:0 rw h 00000000h base register 1 18
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 178 01.00 ________________________________________ ________________________________________ ________________________________________ ________________________________________ ________________________________________ 18h ad. bit type default value register name page 18h 31:0 h 00000000h base address register 2 (not used) 18 1ch ad. bit type default value register name page 1ch 31:0 h 00000000h base address register 3 (not used) 18 20h ad. bit type default value register name page 20h 31:0 h 00000000h base address register 4 (not used) 19 24h ad. bit type default value register name page 24h 31:0 h 00000000h base address register 5 (not used) 19
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 179 01.00 ________________________________________ ________________________________________ ________________________________________ 28h ad. bit type default value register name page 28h 31:0 0000 02c0 cardbus cis pointer 20 31:28 h 0000b rom image number 20 27:3 h 000054h address space offset 20 2:0 h 000b address space indicator 21 2ch ad. bit type default value register name page 2ch 31:20 19:16 e pe 000h pinstrap value or eeprom- value subsystem id 21 15:0 pe pinstrap value or eeprom- value subsystem vendor id 21
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 180 01.00 ________________________________________ ________________________________________ ________________________________________ ________________________________________ 30h ad. bit type default value register name page 30h 31:0 h 00000000h reserved 190 34h ad. bit type default value register name page 34h 31:8 h 00h reserved 132 7:0 h 40h capabilities pointer 132 38h ad. bit type default value register name page 38h 31:0 h 00000000h reserved 190 3ch ad. bit type default value register name page 3ch 31:24 e 00h max_lat 191 23:16 e 00h min_gnt 191 15:8 h 01h interrupt pin 191
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 181 01.00 ________________________________________ 7:0 rw ffh interrupt line 191 3ch (cont ? d) ad. bit type default value register name page 40h ad. bit type default value register name page 40h 31:0 1222 0001 power management capabilities (pmc) 133 31:30 29:28 27 e e e 00b 01b 0b pme_support 133 26 e 0b d2_support 133 25 e 1b d1_support 133 24:22 e 000b aux current 133 21 e 1b dsi 133 20 h 0b reserved 133 19 e 0b pme clock 133 18:16 e 010b version the value 010b indicates that the device complies with the revision 1.1 of the pci power management interface specification. 133 15:8 h 00h next item ptr 133 7:0 h 01h capability id 133
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 182 01.00 ________________________________________ ________________________________________ 44h ad. bit type default value register name page 44h 31:24 h 00h data register 137 23:16 h 00h pmcsr_bse bridge support extensions 137 15 rc 0b pme status 137 14:13 h 00b data scale 137 12:9 rw 0h data select 137 8 rw 0b pme_en 137 7:2 h 00h reserved 137 1:0 rw 00b power state 137 48h ad. bit type default value register name1 page 48h 31:0 power data register 1 140 31:30 h 00b reserved 140 29:28 h/ew 00b data_scale in data_select = 2 140 27:20 h/ew 00h data in data_select = 2 140 19:18 h/ew 00b data_scale in data_select = 1 140 17:10 h/ew 00h data in data_select = 1 140
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 183 01.00 ________________________________________ ________________________________________ 9:8 h/ew 00b data_scale in data_select = 0 140 7:0 h/ew 00h data in data_select = 0 140 48h (cont ? d) ad. bit type default value register name1 page 4ch ad. bit type default value register name page 4ch 31:0 power data register 2 142 31:30 h 00b reserved 142 29:28 e 00b data_scale in data_select = 5 142 27:20 e 00h data in data_select = 5 142 19:18 e 00b data_scale in data_select = 4 142 17:10 e 00h data in data_select = 4 142 9:8 e 00b data_scale in data_select = 3 142 7:0 e 00h data in data_select = 3 142
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 184 01.00 ________________________________________ ________________________________________ ________________________________________ 50h ad. bit type default value register name page 50h 31:0 power data register 3 144 31:20 h 000h reserved 144 19:18 e 00b data_scale in data_select = 7 144 17:10 e 00h data_value in data_select = 7 144 9:8 e 00b data_scale in data_select = 6 144 7:0 e 00h data_value in data_select = 6 144 54h ad. bit type default value register name page 54h 31:0 h 00h cardbus cis 192
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 185 01.00 11.3 registers which do not occur elsewhere in the data sheet ________________________________________ ________________________________________ 00h bit 31:16 device id type e d efault value 2104h description identifies the pita-2 within all pci devices from siemens semiconductors. bit 15:0 vendor id type e d efault value 110ah description 110a is the vendor id of siemens ag. 04h bit 31:0 pci status register d efault value 02900000h bit 31 parity_error_detected type rc d efault value 0b description this bit is set, if a parity error is detected during a transaction with the pita-2. this is done independently from the status of the ? parity error response ? bit.
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 186 01.00 bit 24 data_parity_error_reported type rc d efault value 0b description the pci master asserts this bit if it detects the perr signal on the pci bus asserted during a pci transaction initiated by itself. bit 22 user_defined_functions type h value 0b description the pita-2 has no user defined functions. bit 21 66_mhz_capability type h value 0b description the pita-2 is not a 66 mhz device (0 - 33 mhz supported.) bit 20 capabilities type e d efault value 1b description if this bit is set, the pci device has additional capabilities defined in the pci configuration space header. additional capabilities can be found in the cap_ptr under address 34h. 04h (cont ? d)
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 187 01.00 bit 19:16 reserved type h d efault value 0000b description bit 15:0 command register bit 15:10 reserved type h d efault value 000000b description bit 7 address/data_stepping_enable type h d efault value 0b description not used bit 6 parity_error_response type rw d efault value 0b description if this bit is set to ? 1 ? , the pci interface reports data parity errors by asserting the perr signal. 04h (cont ? d)
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 188 01.00 ________________________________________ ________________________________________ bit 5:3 type h value 000b description the pita-2 does not support the special cycle command. the pita-2 does not generate memory write and invalidate transactions. the pita-2 does not support vga palette snooping. bit 0 i/o_access_enable type h d efault value 0b description the pci interface does not support i/o commands. 04h (cont ? d) 08h bit 31:8 class_code type h or ew d efault value 028 000h description pci network device bit 7:0 revision id type h d efault value 02h description revision of the pci device
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 189 01.00 ________________________________________ ________________________________________ 0ch bit 31:24 bist type h d efault value 00h description the pita-2 has no built-in self test. bit 23:16 header_type type h d efault value 00h description bit 15:8 master_latency_timer type h d efault value 00h description unused bit 7:0 cache_line_size type h d efault value 00h description the pita-2 does not support the cache line size register because it supports only single data transactions.
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 190 01.00 ________________________________________ ________________________________________ ________________________________________ 30h bit 31:0 reserved type h d efault value 0000 0000h description reserved 38h bit 31:0 reserved type h d efault value 0000 0000h description
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 191 01.00 ________________________________________ ________________________________________ 3ch bit 31:24 max_lat type e d efault value 00h description set to ? 0 ? because only single data transactions are supported. bit 23:16 mint_gnt type e d efault value 00h description set to ? 0 ? because only single data transactions are supported. bit 15:8 interrupt_pin type h d efault value 01h description as a single function device, the pita-2 uses the inta signal. bit 7:0 interrupt_line type rw d efault value ffh description these bits show the interrupt line which is used by this system. for a x86 system the value ff means unknown. these registers are written during the initialization of the operating system.
psb 4610 configuration space register of the pita-2 preliminary d ata sheet 192 01.00 ________________________________________ ________________________________________ 54h bit 31:0 cardbus_cis type h value 00h description not supported by pita-2
psb 4610 internal register of the pita preliminary d ata sheet 193 01.00 12 internal register of the pita ________________________________________ ________________________________________ overview page description of the register types 194 internal register 195 registers which do not occur elsewhere in the data sheet 202
psb 4610 internal register of the pita preliminary d ata sheet 194 01.00 12.1 description of the register types ________________________________________ ________________________________________ description of the register types type description r read only rc read clear these bits are set by the internal logic these bits can be read out and reset by writing logical ? 1 ? to them writing logical ? 0 ? doesn ? t influence the states of these bits rw read write these bits can be read out and written via the pci bus
psb 4610 internal register of the pita preliminary d ata sheet 195 01.00 12.2 internal register ________________________________________ 00h ad. bit type default value register name page 00h 31:0 00000000h icr - interrupt control register 202 31:29 r 000b reserved 202 28 rw 0b eeprom_control_int_en 121 27 rw 0b retry_counter_down_ int_en 31 26 rw 0b fifo_overflow_empty_ int_en 41 25 rw 0b dma_write_counter_ overflow_int_en 41 24 rw 0b dma_write_counter_int_ en 41 23:18 r 000000b reserved 202 17 rw 0b int0_en 202 16 rw 0b int0_pol 202 15:13 r 000b reserved 202 12 rc 0b eeprom_control_int 121 11 rc 0b retry_counter_int 31 10 rc 0b fifo_overflow_empty_ int 41 9 rc 0b dma_write_counter_ overflow_int 41 8 rc 0b dma_write_counter_int 41
psb 4610 internal register of the pita preliminary d ata sheet 196 01.00 ________________________________________ ________________________________________ 7:6 r 0b reserved 202 5 rc 0b gp3_int 101 4 rc 0b gp2_int 101 3 rc 0b gp1_int 101 2 rc 0b gp0_int 101 1rc0b int0 202 00h (cont ? d) ad. bit type default value register name page 04h ad. bit type default value register name page 04h 31:0 00000000h dma control register 43 31:09 r 0000000h reserved 43 8rw0b dma start 43 7:6 r 00b reserved 43 5:0 rw 000000b dma select - all modes iom-2 mode 1 iom-2 mode 2 iom-2 mode 3 single modem mode v2.1 single modem mode v3.x dual modem+voice mode 43 48 52 55 63 67 75
psb 4610 internal register of the pita preliminary d ata sheet 197 01.00 ________________________________________ ________________________________________ ________________________________________ ________________________________________ 08h ad. bit type default value register name page 08h 31:12 11:0 rw r 00000h 000h circular buffer start address 45 0ch ad. bit type default value register name page 0ch 31:00 r 00000000h actual circular buffer pointer 45 10h ad. bit type default value register name page 10h 31:0 00000000h alis command register 1 67 31:25 r 00h reserved 67 24 rw 0b new_alis_command_1 67 23:16 rw 00h alis_received_data_1 67 15:8 rw 00h alis_command_1 67 7:0 rw 0b alis_transmit_data_1 67
psb 4610 internal register of the pita preliminary d ata sheet 198 01.00 ________________________________________ ________________________________________ 14h ad. bit type default value register name page 14h 31:0 00000000h alis command register 2 70 32:25 r 000h reserved 70 24 rw 0b new_alis_command_2 70 23:16 rw 00h alis_received_data_2 70 15:8 rw 00h alis_command_2 70 7:0 rw 00h alis_transmit_data_2 70 18h ad. bit type default value register name page 18h 31:0 00000000h gp i/o interface control register 102 31:28 r 0h reserved 102 27 rw 0b gp3_int_en 102 26 rw 0b gp2_int_en 102 25 rw 0b gp1_int_en 102 24 rw 0b gp0_int_en 102 23:20 r 0000b reserved 102 19 rw 0b gp3_out_en 102 18 rw 0b gp2_out_en 102
psb 4610 internal register of the pita preliminary d ata sheet 199 01.00 ________________________________________ 17 rw 0b gp1_out_en 102 16 rw 0b gp0_out_en 102 15:12 r 0000b reserved 102 11 r - gp3_in 102 10 r - gp2_in 102 9 r - gp1_in 102 8 r - gp0_in 102 7:4 r 0000b reserved 102 3 rw 0b gp3_out 102 2 rw 0b gp2_out 102 1 rw 0b gp1_out 102 0 rw 0b gp0_out 102 18h (cont ? d) ad. bit type default value register name page 1ch ad. bit type default value register name page 1ch 31:0 00000000h misc - miscellaneous register 59 31 rw 0b iom b1 masking 59 30 rw 0b iom b2 masking 59 29 rw 0b iom mon0/ic1 masking 59 28 rw 0b iom d+c/i0+mr+mx / ic2 masking 59
psb 4610 internal register of the pita preliminary d ata sheet 200 01.00 ________________________________________ 27 rw 1b serial interface buffer mode 204 26 rw 0b parallel interface mode 78 25 rw 1b s oft res et serial inter face 204 24 rw 0b soft reset parallel interface 78 23:16 rw 00h retry count register 32 15:12 r 0000b reserved 204 11:0 rw 0000h dma write count register 46 1ch (cont ? d) ad. bit type default value register name page 20h ad. bit type default value register name page 20h 31:0 00000000h serial clock select register 31:2 r 00000000h reserved 1 rw 0b dcl_out_en 49 52 55 64 72 0 rw 0b serial_clock_sel 49 52 55 64 72
psb 4610 internal register of the pita preliminary d ata sheet 201 01.00 ________________________________________ ________________________________________ ________________________________________ 24h ad. bit type default value register name page 24h 31:0 00000000h eeprom control register 121 31:25 r 0000h reserved 121 24 rw 0b eeprom start 121 23:16 rw 00h eeprom command 121 15:8 rw 00h eeprom byte address 121 7:0 rw 00h eeprom data 121 28h ad. bit type default value register name page 28h 31:0 00000000h dma test register 204 31:01 r 00000000h reserved 204 0 rw 0b loop_back_mode 77
psb 4610 internal register of the pita preliminary d ata sheet 202 01.00 12.3 registers which do not occur elsewhere in the data sheet ________________________________________ 00h bit 31:0 icr - interrupt control register d efault value 00000000h description the interrupt enable bits for gp3-0 are placed in the gp i/o interface control register. all interrupt enables are high active: int_en= ? 0 ? -> corresponding interrupt (bit) is disabled int_en= ? 1 ? -> corresponding interrupt (bit) is enables bit 31:29 reserved type r value 000b bit 23:18 reserved type r value 000000b bit 17 int0_en type rw d efault value rw description enable for the int0 interrupt bit.
psb 4610 internal register of the pita preliminary d ata sheet 203 01.00 ________________________________________ bit 16 int0_p ol type rw d efault value 0b description polarity of int0 active level 0: l-level 1: h-level bit 23:18 reserved type r value 000000b bit 1 int0 type rc d efault value 0b description an interrupt is detected on pin int0 . bit 0 reserved type r value 0b 00h (cont ? d)
psb 4610 internal register of the pita preliminary d ata sheet 204 01.00 ________________________________________ ________________________________________ ________________________________________ 1ch bit 27 serial interface buffer mode type rw value 1b description 0: the txd pin is configured as push/pull output pin. 1: the txd pin is configured as open drain output pin. bit 25 soft reset serial interface type rw d efault value 1b description 0: activates the low active reset signal srst to the application. 1: deactivates the reset signal srst to the application. before asserting this bit the dma_start bit has to be reset. 28h bit 31:0 dma test register d efault value 00000000h bit 31:1 reserved type r d efault value 00000000h
psb 4610 abbreviations preliminary d ata sheet 205 01.00 13 abbreviations ac alternating current. a/d analog to digital. adc analog to digital converter. ale address latch enable. alis analog line interface solution. chip set consisting of psb4595 and psb4596. dc direct current. dcl double bit clock. (in this context, only in the iom-2 modes of the serial interface of the pita, single bit in all other modes). dma direct memory access. dd data downstream. du data upstream. eeprom = e 2 prom electrically erasable programmable read only memory. fifo rx fifo tx fifo firs t in firs t out. fs c fram e s ync. i/o in/out. iom isdn oriented modular. isdn integrated services digital network. msb most significant bit. pita pci interface for telephony/data applications. pci peripheral component interconnect. rxd receive direction. txd transmit direction.
psb 4610 index semiconductor group 206 preliminary data sheet 01.00 14 index a a bsolute max im um ratings 167 a lis v 2.1 configuration after reset 63 connection to the pita-2 118 a lis v 3.x configuration after reset 66 b base address register 16 bar 0 17 bar 1 18 structure of the address space 16 c configuration space register power management 34h 132 40h 133 44h 137, 140, 142, 144 reference table 175 d dc characteristics 168 dma algorithm 38 dma controller 36 dual modem/modem+voice mode 73 g general purpose i/o interface 97 input mode 107 interrupt mode 111 output mode 109 i interfaces general purpose i/o interface 97 parallel interface 78 serial dma interface 34 spi e epr om inter face 115 internal register 00h 195 20h 200 24h 201 dma controller 00h 41 04h 43, 45, 63, 67, 69, 75 08h 45 0ch 45, 46, 77, 78, 102 1ch 46 gp i/o interface 00h 101 18h 102 loopback mode 28h 77 parallel interface 1ch 78 reference table 195 retry counter 00h 31 1ch 32 single modem mode v2.1 20h 49, 52, 55, 64, 72 spi e ep rom inter face 00h 67, 70, 121 24h 121 interrupt control register 31 iom-2 mode 1 47 iom-2 mode 2 50 iom-2 mode 3 53 iom-2 modes general description 56 masking of iom-2 timeslots 58 selection of iom-2 timeslots 56 l loopback mode 76 m multiplexed mode
psb 4610 index semiconductor group 207 preliminary data sheet 01.00 read transaction 88 write transaction 87 n non multiplexed mode read transaction 86 write transaction 84 p parallel interface 78 pci bus pinning 158 pci commands 23 pci configuration space 11 acc ess to the 15 construction of 13 pci master controller 23 pci target controller 23 pinning description of pin types 157 gp i/o inter face 162 parallel interfaces 159 power supply 164, 165 serial interface 161 special eeprom signals 163 pinstrapping 151 power management 123 power management states 126 r res et 149 s serial dma interface 34 single modem mode v2.1 61 configuration after reset 62 single modem mode v3.x 65 configuration after reset 66 spi eeprom interface 115 t timing 89 timing diagram ale after internal softreset 82 ale after setting the parallel interface mode bit 83 ale after system reset 81 burst read 25 burst write 27 dual modem/modem+voice mode 74 fast back to back 29 gp i/o interface input mode 107 interrupt mode 111 output mode 110 iom-2 all modes 56 iom-2 mode 1 48 iom-2 mode 2 51 iom-2 mode 3 54 loopback mode 76 parallel interface multiplexed address 94 non mulitplexed address 95 read 94 write 94 single modem mode v2.1 61 single modem mode v3.x 65 spi e ep rom inter face 119 transaction disconnect 89 transaction termination 92 v vendor id 151

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